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rev.1.06 mar 07, 2008 page 1 of 59 rej03b0140-0106 description the 7545 group is the 8-bit microcomputer based on the 740 family core technology. the 7545 group has an 8-bit timer, power-on reset circuit and the voltage drop detection circu it. also, function set rom is equipped. features ? basic machine-language instructions ............ ......... ............. 71 ? the minimum instruction execution time .................... 2.00 s (at 4 mhz oscillati on frequency for the sh ortest instruction) ? memory size rom ........................................ 4k to 60k bytes ram .......... ........... ......... ......... ..... 256, 512 bytes ? programmable i/o ports ...................................................... 25 ? key-on wakeup input ...... ........... ........... ........... ........... 8 inputs ? led output port ...................................................................... 8 ? interrupts.................................................... 7 sources, 7 vectors ? timers .......................................................................... 8-bit 3 ? carrier wave generating circui t .......1 channel (8-bit timer 2) ? clock generating circuit ........................................ built-in type (connect to external ceramic resonator or quartz-crystal oscillator) ? watchdog timer .........................................................16-bit 1 ? power-on reset circuit............................................ built-in type ? voltage drop detection circuit................................ built-in type ? power source voltage x in oscillation frequenc y at ceramic/quartz- crystal oscillation at 4 mhz .......................................... 1.8 to 3.6 v ? power dissipation .......................................................... 1.8mw ? operating temperature range .................................? 20 to 85 c application remote control transmit. fig. 1 pin configuration (plqp0032gb-a type) package type: plqp0032gb-a (32p6u-a) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 8 7 6 5 3 4 v cc cnv ss p2 5 (led 5 ) p0 3 /key 3 p0 0 /key 0 p0 2 /key 2 p0 1 /key 1 p0 4 /key 4 p3 7 p3 6 p3 5 m37545gx-xxxgp m37545gxgp p2 6 (led 6 ) p2 7 (led 7 ) p4 2 /carr v ddr reset 12 p2 3 (led 3 ) p2 4 (led 4 ) p2 2 (led 2 ) p2 1 (led 1 )/int 1 p2 0 (led 0 )/int 0 p0 7 /key 7 p0 6 /key 6 p0 5 /key 5 x out x in v ss p3 0 p3 1 p3 2 p3 3 p3 4 24 23 22 21 20 19 18 17 pin configuration (top view) 7545 group single-chip 8-bit cmos microcomputer rej03b0140-0106 rev.1.06 mar 07, 2008 http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 2 of 59 rej03b0140-0106 7545 group fig. 2 pin configuration (plsp0032jb-a type) fig. 3 pin configuration (42s1m type) p2 1 (led 1 )/int 1 32 m37545gxkp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p4 2 /carr reset v cc x in x out v ss p3 0 p2 0 (led 0 )/int 0 p0 7 /key 7 p0 6 /key 6 p0 5 /key 5 p0 4 /key 4 p0 3 /key 3 p0 2 /key 2 p0 1 /key 1 p3 7 p0 0 /key 0 p3 5 p3 4 p3 3 p3 2 p3 1 p3 6 cnv ss v ddr package type: plsp0032jb-a pin configuration (top view) package type: 42s1m p2 2 (led 2 ) 42 m37545rlss 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc p2 3 (led 3 ) p2 4 (led 4 ) nc p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p4 0 (led 8 ) p4 2 /carr nc nc v ddr reset p4 1 (led 9 ) p2 1 (led 1 )/int 1 p2 0 (led 0 )/int 0 p0 7 /key 7 p0 6 /key 6 p0 5 /key 5 p0 4 /key 4 p0 3 /key 3 p0 2 /key 2 p0 1 /key 1 p0 0 /key 0 p3 6 nc p3 5 p3 4 p3 3 p3 7 26 25 24 23 22 17 18 19 20 21 cnv ss v cc x in x out v ss p3 2 p3 1 p3 0 p1 1 p1 0 pin configuration (top view) http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 3 of 59 rej03b0140-0106 7545 group table 1 performance overview (1) parameter function number of basic instructions 71 instruction execution time 2.00 s (minimum instruction) memory sizes rom m37545g1 4096 bytes 8 bits m37545g2 8192 bytes 8 bits m37545g4 16384 bytes 8 bits m37545g6 24576 bytes 8 bits m37545g8 32768 bytes 8 bits m37545gc 49152 bytes 8 bits m37545gf 61440 bytes 8 bits ram m37545g1/g2 ram1: 240 bytes 8 bits, ram2: 16 bytes 8 bits m37545g4/g6/g8/gc/gf ram1: 384 bytes 8 bits, ram2: 128 bytes 8 bits i/o port p0 0 ? p0 7 i/o ? 1-bit 8 ? cmos compatible input level ? cmos 3-state output structure ? whether the pull-up function/key-on wak eup function is to be used or not can be determined by program. p1 0 , p1 1 i/o (rlss-only pin) ? 1-bit 2 ? cmos compatible input level ? the output structure can be switched to n-channel open-drain or cmos by software. p2 0 ? p2 7 i/o ? 1-bit 8 ? cmos compatible input level ? the output structure can be switched to n-channel open-drain or cmos by software. ? p2 can output a large current for driving led. ?p2 0 and p2 1 are also used as int 0 and int 1 , respectively. p3 0 ? p3 7 i/o ? 1-bit 8 ? cmos compatible input level ? the output structure can be switched to n-channel open-drain or cmos by software. p4 0 , p4 1 i/o (rlss-only pin) ? 1-bit 2 ? cmos compatible input level ? cmos 3-state output structure p4 2 i/o ? 1-bit 1 ? cmos compatible input level ? cmos 3-state output structure ? carrier wave output pin for remote-control transmitter timer timer 1 8-bit timer with timer 1 latch count source is prescaler output. timer 2 8-bit timer with timer 2 primary latch and timer 2 secondary latch count source can be selected from f(x in )/16, f(x in )/8, f(x in )/2 or f(x in )/1. timer 3 8-bit timer with timer 3 latch count source can be selected from f(x in )/16, f(x in )/8 or f(x in )/2 or carrier wave output. carrier wave generating circuit remote-control wa veform is generated by using timer 2 and timer 3. 455 khz carrier wave generating mode is available. watchdog timer 16-bit 1 power-on reset circuit built-in voltage drop detection circuit (not av ailable for rlss) typ. 1.75 v (ta=25 c) interrupt source 7 sources (external 3, timer 3, software) function set rom area function set rom function set rom is assigned to address ffda 16 . enable/disable of watchdog timer and stp instruction can be selected. valid/invaid of voltage drop detection circuit can be selected. rom code protect rom code prot ect is assigned to address ffdb 16 . read/write the built-in qzrom by seri al programmer is disabled by setting ? 00 ? to rom code protect. device structure cmos silicon gate package 32-pin plastic mol ded lqfp (plqp0032gb-a) 32-pin plastic molded ssop (plsp0032jb-a) operating temperature range ? 20 to 85 c power source voltage f(x in ) = 4 mhz 1.8 to 3.6 v http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 4 of 59 rej03b0140-0106 7545 group table 2 performance overview (2) parameter function power dissipation at cpu active typ. 0.6 ma (f(x in )=4 mhz, vcc=3.0 v, output transistors ?off? ) at wit instruction executed typ. 0.3 ma (f(x in )=4 mhz, vcc=3.0 v, output transistors ?off? , in wit state, function except timer 1 disabled) at stp instruction executed typ. 0.1 a (ta = 25 c, v cc v ddr v cc ? 0.6 v, output transistors ?off?, in stp state, all oscillation stopped) during reset by voltage drop detection circuit typ. 0.1 a (ta = 25 c, v ddr = 1.1 v, 1.8 v v cc 0v) http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 5 of 59 rej03b0140-0106 7545 group fig. 4 functional block diagram (plqp0032gb-a package) p 2 ( 8 ) 1 3 1 2 9 3 2 3 0 2 8 p 0 ( 8 ) 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 r a m r o m a x y s p c l p c h p s c p u v s s 1 1 v c c 8 0 p 3 ( 8 ) 3 2 0 p 4 ( 1 ) 4 t i m e r 1 ( 8 ) r e s e t r e s e t r e s e t i / o p o r t p 3 i / o p o r t p 0 f u n c t i o n a l b l o c k d i a g r a m ( p a c k a g e : p l q p 0 0 3 2 g b - a ) w a t c h d o g t i m e r c a r r i e r w a v e g e n e r a t i n g c i r c u i t p r e s c a l e r 1 ( 8 ) v o l t a g e d r o p d e t e c t i o n c i r c u i t p o w e r - o n r e s e t c i r c u i t i / o p o r t p 2 i / o p o r t p 4 1 7 1 5 1 3 1 6 1 4 1 2 1 9 1 8 i n t 0 i n t 1 k e y - o n w a k e u p p r e s c a l e r 2 ( 8 ) p r e s c a l e r 3 ( 8 ) v d d r 5 c l o c k o u t p u t x o u t 1 0 9 c l o c k i n p u t x i n c l o c k g e n e r a t i n g c i r c u i t r e s e t 6 r e s e t i / o 7 c n v s s http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 6 of 59 rej03b0140-0106 7545 group fig. 5 functional block diagram (plsp0032jb-a package) p 2 ( 8 ) 5 3 1 4 2 3 2 p 0 ( 8 ) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 3 r a m r o m a x y s p c l p c h p s c p u v s s 1 5 v c c 1 2 0 p 3 ( 8 ) 7 6 0 p 4 ( 1 ) 8 t i m e r 1 ( 8 ) r e s e t r e s e t r e s e t i / o p o r t p 3 i / o p o r t p 0 f u n c t i o n a l b l o c k d i a g r a m ( p a c k a g e : p l s p 0 0 3 2 j b - a ) w a t c h d o g t i m e r c a r r i e r w a v e g e n e r a t i n g c i r c u i t p r e s c a l e r 1 ( 8 ) v o l t a g e d r o p d e t e c t i o n c i r c u i t p o w e r - o n r e s e t c i r c u i t i / o p o r t p 2 i / o p o r t p 4 2 1 1 9 1 7 2 0 1 8 1 6 2 4 2 2 i n t 0 i n t 1 k e y - o n w a k e u p p r e s c a l e r 2 ( 8 ) p r e s c a l e r 3 ( 8 ) v d d r 1 0 c l o c k o u t p u t x o u t 1 4 1 3 c l o c k i n p u t x i n c l o c k g e n e r a t i n g c i r c u i t r e s e t 9 r e s e t i / o 1 1 c n v s s http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 7 of 59 rej03b0140-0106 7545 group pin description table 3 pin description pin name function function expect a port function v cc , v ss power source ? apply voltage of 1.8 to 3.6v to v cc , and 0 v to v ss . v ddr power source ? power source pin only for ram2. when this pin is used, con nect an approximately 0.1 f bypass capacitor across the v ss line and the v ddr line. when not used, connect it to v ss . cnv ss cnv ss ? chip operating mode control pin, wh ich is always connected to vss. reset reset i/o ? an n-channel open-drain i/o pin for a system reset. this pin has a pull-up transistor. when the watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the reset pin outputs "l" level. x in clock input ? input and output pins fo r main clock generating circuit ? connect a ceramic resonator or quar tz-crystal oscillator between the x in and x out pins. x out clock output p0 0 /key 0 ? p0 7 /key 7 i/o port p0 ? 8-bit i/o port. ? i/o direction register allows each pin to be individually programmed as either input or output. ? cmos compatible input level ? cmos 3-state output structure ? whether the pull-up functi on/key-on wakeup function is to be used or not can be determined by program. ? key-input (key-on wake up interrupt input) pins p1 0 , p1 1 i/o port p1 ? 2-bit i/o port having almost the same function as p0. ? cmos compatible input level ? the output structure can be switched to n-channel open-drain or cmos by software. note: rlss-only pins p2 0 (led 0 )/int 0 p2 1 (led 1 )/int 1 p2 2 (led 2 ) ? p2 7 (led 7 ) i/o port p2 ? 8-bit i/o port having almost the same function as p0. ? cmos compatible input level ? the output structure can be switched to n-channel open-drain or cmos by software. ? p2 can output a large current for driving led. ? interrupt input pins p3 0 ? p3 7 i/o port p3 ? 8-bit i/o port ? i/o direction register allows each pin to be i ndividually programmed as either input or output. ? cmos compatible input level ? the output structure can be switched to n- channel open-drain or cmos by software. p4 0 (led 8 ), p4 1 (led 9 ) i/o port p4 ? 2-bit i/o port having almost the same function as p0. ? cmos compatible input level ? cmos 3-state output structure note: rlss-only pins p4 2 /carr ? 1-bit i/o port ? cmos compatible input level ? cmos 3-state output structure ? carrier wave output pin for remote- control transmit http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 8 of 59 rej03b0140-0106 7545 group group expansion we are planning to expand the 7545 group as follow: memory type support for qzrom version and emulator mcu. memory size ? rom size ..................................................... 4 k to 60 k bytes ? ram size ................ ............ ........... ......... .......... 256, 512 bytes packages ? plqp0032gb-a ... 0.8 mm-pitch 32-pin plastic molded lqfp ? plsp0032jb-a ... 0.65 mm-pitch 32 -pin plastic molded ssop ? 42s1m ........................... 42-pin shrink ceramic piggy back fig. 6 memory expansion plan currently supported produc ts are listed below. 256 512 32k 24k 16k 0 m37545g8 ram size (bytes) rom size (bytes) m37545g6 m37545g4 8k 60k 48k 4k m37545g2 m37545g1 m37545gf m37545gc **: under development ** ** ** ** ** ** ** table 4 list of supported products part number rom size (bytes) rom size for user ( ) ram size (bytes) package remarks m37545g1kp 4096 (3966) 256 plsp0032jb-a qzrom version (blank) m37545g2kp 8192 (8062) plsp0032jb-a qzrom version (blank) m37545g4-xxxgp 16384 (16254) 512 plqp0032gb-a qzrom version m37545g4gp qzrom version (blank) m37545g4kp plsp0032jb-a qzrom version (blank) m37545g6-xxxgp 24576 (24446) plqp0032gb-a qzrom version m37545g6gp qzrom version (blank) m37545g6kp plsp0032jb-a qzrom version (blank) m37545g8-xxxgp 32768 (32638) plqp0032gb-a qzrom version m37545g8gp qzrom version (blank) m37545g8kp plsp0032jb-a qzrom version (blank) m37545gc-xxxgp 49152 (49022) plqp0032gb-a qzrom version m37545gcgp qzrom version (blank) m37545gckp plsp0032jb-a qzrom version (blank) m37545gf-xxxgp 61440 (61310) plqp0032gb-a qzrom version m37545gfgp qzrom version (blank) m37545gfkp plsp0032jb-a qzrom version (blank) m37545rlss 42s1m emulator mcu http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 9 of 59 rej03b0140-0106 7545 group functional description central processing unit (cpu) the mcu uses the standard 740 fa mily instruction set. refer to the table of 740 family addres sing modes and machine-language instructions or the series 740 user?s manual for details on each instruction set. machine-resident 740 family in structions are as follows: 1. the fst and slw instru ctions cannot be used. 2. the mul and div instructions can be used. 3. the wit instruction can be used. 4. the stp instruction can be used. this instruction cannot be used while cpu operates by an on- chip oscillator. [accumulator (a)] the accumulator is an 8-bit regist er. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x), index register y (y)] both index register x and index re gister y are 8-bit registers. in the index addressing modes, the value of the operand is added to the contents of register x or register y and specifies the real address. when the t flag in the processor status register is set to ?1?, the value contained in index register x becomes the address for the second operand. [stack pointer (s)] the stack pointer is an 8-bit regi ster used during subroutine calls and interrupts. the stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. the lower eight bits of the stack address are determined by the contents of the stack pointer. the upper eight bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is ?0?, then the ram in the zero page is used as the stack area. if the stack page selection bit is ?1?, then ram in page 1 is used as the stack area. the stack page selection bit is located in the sfr area in the zero page. note that the initial value of the stack page selection bit varies with each microcomputer type. also some microcomputer types have no stack page selection bit and the upper eight bits of the stack a ddress are fixed. the operations of pushing register cont ents onto the stack and popping them from the stack are shown in figure 8. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 7 740 family cp u register structure b7 b0 x b7 b0 s b7 b0 y b7 b0 pc l processor status register (ps) carry flag b7 b0 b7 b0 a b15 pc h zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag program counter stack pointer index register y index register x accumulator c z i d b t v n http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 10 of 59 rej03b0140-0106 7545 group fig. 8 register push and pop at in terrupt generation and subroutine call execute jsr on-going routine m (s) (pc h ) m (s) (pc l ) execute rts (pc l ) m (s) (s) (s + 1) (s) (s + 1) (pc h ) m (s) subroutine restore return address store return address on stack m (s) (ps) execute rti (ps) m (s) interrupt service routine restore contents of processor status register m (s) (pc h ) (s) (s - 1) m (s) (pc l ) (pc l ) m (s) (pc h ) m (s) restore return address i flag ?0? to ?1? fetch the jump vector store return address on stack store contents of processor status register on stack interrupt request (note) note : the condition to enable the interrupt interrupt enable bit is ?1? interrupt disable flag is ?0? (s) (s - 1) (s) (s - 1) (s) (s + 1) (s) (s + 1) (s) (s + 1) (s) (s - 1) (s) (s - 1) table 5 push and pop instructions of accumulator or processor status register push instruction to stack p op instruction from stack accumulator pha pla processor status register php plp http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 11 of 59 rej03b0140-0106 7545 group [processor status register (ps)] the processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. branch operations can be performed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decima l mode, the z, v, n flags are not valid. after reset, the interrupt disable (i) flag is set to ?1?, but all other flags are undefined. since the index x mode (t) and decimal mode (d) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the resu lt of an immediate arithmetic operation or a data transfer is ?0 ?, and cleared if the result is anything other than ?0?. bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruct ion. interrupts are disabled when the i flag is ?1?. when an interrupt occurs, this flag is automatically set to ?1? to prevent other interrupts from interfering until the current interrupt is serviced. bit 3: decimal mode flag (d) the d flag determines whether additions and s ubtractions are executed in binary or decimal. binary arithmetic is executed when this flag is ?0?; decimal arithmetic is executed when it is ?1?. decimal correction is automati c in decimal mode. only the adc and sbc instru ctions can be used for decimal arithmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always ?0?. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto th e stack with the break flag set to ?1?. the saved processor stat us is the only place where the break flag is ever set. bit 5: index x mode flag (t) when the t flag is ?0?, arithmetic operations are performed between accumulator and memory . when the t flag is ?1?, direct arithmetic operations a nd direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to - 128. when the bit instructio n is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 6 set and clear instructions of each bit of processor status register c flag z flag i flag d flag b flag t flag v flag n flag set instruction sec ? sei sed ? set ?? clear instruction clc ? cli cld ? clt clv ? http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 12 of 59 rej03b0140-0106 7545 group [cpu mode regi ster (cpum)] the cpu mode register contains the stack page selection bit. this register is allocated at address 003b 16 . for this product, the clock speed of cpu is always f(x in )/4. fig. 9 structure of cpu mode register processor mode bits (note) b1 b0 0 0 single-chip mode 01 10 11 not available b7 b0 note : the bit can be rewritten only once after releasing reset. after rewriting, it is disabled to write any data to this bit. however, by reset the bit is initialized and can be rewritten, again. it is not disabled to write any data to this bit for emulator mcu ?gm37545rlss .?h cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0:0page 1:1page clock division ratio selection bits b7 b6 0 0 : not available 0 1 : not available 10:f( ) = f(x in )/4 1 1 : not available not used (returns ?g0?h when read) http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 13 of 59 rej03b0140-0106 7545 group memory special function register (sfr) area the sfr area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage a nd for a stack area of subroutine calls and interrupts. ram cons ists of ram1 and ram2. the power source for ram1 is supplied from v cc pin. the power source for ram2 is supplied from v ddr pin. note: when the v ddr pin is used, connect an approximately 0.1 f bypass capacitor across the v ss line and the v ddr line. when not used, connect it to v ss . rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. interrupt vector area the interrupt vector area contai ns reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers(sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special pa ge addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. function set rom area [renesas shipment test area] figure 10 shows the assignment of function set rom area. the random data are set to the renesas shipment test areas (addresses ffd4 16 to address ffd9 16 ). do not rewrite the data of these areas. when the checksum is included in the user program, avoid assigning it to these areas. [function set rom data] fsrom function set rom da ta (address ffda 16 ) is used to set modes of peripheral functions. by setting this area, the operation mode of each peripheral function are se t after system is released from reset. refer to the descriptions of peri pheral functions for the details of operation of peripheral functions. ? watchdog timer ? low voltage de tection circuit this mode setting of peripheral functions cannot be changed by program after system is released from reset. rom code protect ad dress (address ffdb 16 ) address ffdb 16 , which is the reserved rom area of qzrom, is the rom code protect address. ?00 16 ? is written into this address when selecting the protect bit wr ite by using a se rial programmer or selecting protect enabled fo r writing shipment by renesas technology corp.. when ?00 16 ? is set to the rom code protect address, the protect function is enab led, so that reading or writing from/to qzrom is disabled by a serial programmer. as for the qzrom product in blan k, the rom code is protected by selecting the protect bit wr ite at rom writing with a serial programmer. as for the qzrom product sh ipped after writing, ?00 16 ? (protect enabled) or ?ff 16 ? (protect disabled) is written into the rom code protect address when renesas technology corp. performs writing. the writing of ?00 16 ? or ?ff 16 ? can be selected as the rom option setup (referred to as ?mask option setup? in mm) when ordering. 1. because the contents of ram ar e indefinite at reset, set ini- tial values before using. 2. do not access to the reserved area. 3. random data is written into the renesas shipment test area and the reserved rom area. do not rewrite the data in these areas. data of these area may be changed without notice. accordingly, do not include these areas into programs such as checksum of all rom areas. 4. the qzrom values in functi on set rom data set the oper- ating modes of the various peripheral functions after an mcu reset is released. do not fail to set the value for the selected function. bi ts designated with a fixed value of 1 or 0 must be set to th e designated value. 5. emulator mcu: as fo r m37545rlss, set ?010000xx 2 ? to function set rom da ta (address ffda 16 ). also, set ?ff 16 ? to rom code protect (address ffdb 16 ). http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 14 of 59 rej03b0140-0106 7545 group fig. 10 memory map diagram 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram1 rom 16384 c000 16 c080 16 240 012f 16 ffd4 16 wwww 16 16 01cf 16 ram2 24576 a000 16 a080 16 32768 8000 16 8080 16 function set rom area address ffd4 16 ffd5 16 ffd6 16 renesas shipment test area reserved rom area reserved rom area ffd7 16 ffd8 16 ffd9 16 reserved rom area reserved rom area reserved rom area ffda 16 ffdb 16 function set rom data rom code protect ram 2 area ram capacity (bytes) address xxxx 16 ram 1 area ram capacity (bytes) address wwww 16 rom area rom capacity (bytes) address yyyy 16 address zzzz 16 reserved area sfr area disable interrupt vector area reserved rom area (128 bytes) reserved rom area function set rom area 384 01bf 16 128 023f 16 49152 4000 16 4080 16 61440 1000 16 1080 16 4096 f000 16 f080 16 8192 e000 16 e080 16 01c0 16 rom http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 15 of 59 rej03b0140-0106 7545 group fig. 11 memory map of s pecial function register (sfr) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) pull-up control register (pull) key-on wakeup pin selection register (keysel) port output mode selection register (pmod) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer count source set register (tcss) prescaler 1 (pre1) timer 1 (t1) timer 1,2,3 control register (tc123) timer 2 primary (t2p) reserved reserved reserved misrg watchdog timer contro l register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) reserved reserved reserved reserved reserved reserved reserved carrier wave control register (carcnt) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved note : do not access to the sfr area including nothing. port p4 (p4) port p4 direction register (p4d) key-on wakeup edge selection register (keyedge) reserved reserved timer 2 secondary (t2s) timer 3 (t3) reserved reserved reserved reserved reserved reserved reserved reserved reserved http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 16 of 59 rej03b0140-0106 7545 group fig. 12 structure of function set rom area b7 function set rom data (fsrom: address ffda 16 ) b0 watchdog timer disable bit 0: watchdog timer enabled 1: watchdog timer disabled stp instruction function selection bit 0: internal reset occurs at the stp instruction execution 1: system enters into the stop mode at the stp instrcution execution mcu package set bit 0: gp package version 1: kp package version set ?g0?h to this bit. voltage drop detection circuit valid bit 0: voltage drop detection circuit invalid 1: voltage drop detection circuit valid set ?g0?h to this bit. setting the number of pins 0: set ?g0?h to this bit in gp or kp package version 1: set ?g1?h to this bit in the emulator mcu set ?g0?h to this bit. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 17 of 59 rej03b0140-0106 7545 group i/o ports [direction registers] pid the i/o ports have direction regi sters which determine the input/ output direction of each pin. ea ch bit in a direction register corresponds to one pin, and each pin can be set to be input or output. when ?1? is set to the bit corr esponding to a pin, this pin becomes an output port. when ?0 ? is set to the bit, the pin becomes an input port. when data is read from a pin se t to output, not the value of the pin itself but the value of port latc h is read. pins set to input are floating, and permit reading pin values. if a pin set to input is written to , only the port latch is written to and the pin remains floating. [pull-up control register] pull by setting the pull-up cont rol register (address 0016 16 ), port p0 can exert pull-up control by program. however, pins set to output are disconnected from this control and cannot exert pull- up control. [port output mode selection register] pmod by setting the port output mode selection register (address 0017 16 ), cmos output or nch open-drain can be selected for ports p1, p2, p3 by program. fig. 13 structure of pull-up control register fig. 14 structure of port output mode selection register port p0 4 port p0 1 port p0 0 0: pull-up transistor off 1: pull-up transistor on b7 b0 port p0 2 port p0 3 port p0 5 port p0 6 port p0 7 pull-up control register (pull: address 0016 16 , initial value: 00 16 ) table 7 i/o port function table pin name input/output i/o format non-port function related sfrs diagram no. p0 0 ? p0 7 port p0 i/o individual bits ? cmos compatible input level ? cmos 3-state output key input interrupt pull-up control register key-on wakeup pin selection register key-on wakeup edge selection regis- ter (1) p1 0 ? p1 1 port p1 ? cmos compatible input level ? cmos 3-state output or n-channel opendrain rlss-only pin port output mode selection register (2) p2 0 /int 0 p2 1 /int 1 port p2 external interrupt input interrupt edge selection register port output mode selection register (3) p2 2 ? p2 7 port output mode selection register (2) p3 0 ? p3 7 port p3 port output mode selection register (2) p4 0 , p4 1 port p4 ? cmos compatible input level ? cmos 3-state output rlss-only pin (4) p4 2 /carr carrier wave output for remote-control transmitter carrier wave control register (5) port p3 4 ? p3 7 port p2 0 ? p2 3 port p1 0 ? p1 1 0: cmos output 1: nch open-drain b7 b0 port p2 4 ? p2 7 port p3 0 ? p3 3 disable (returns ?0? when read) port output mode selection register (pmod: address 0017 16 , initial value: 00 16 ) http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 18 of 59 rej03b0140-0106 7545 group fig. 15 block diagram of ports (1) (5) port p4 2 (4) ports p4 0 , p4 1 (1) ports p0 0 - p0 7 pull-up control to key input interrupt generating circuit (2) ports p1 0 - p1 1 , p2 2 - p2 7 , p3 0 - p3 7 key-on wakeup pin selection (3) ports p2 0 , p2 1 port output mode switch to int 0 , int 1 interrupt circuit port output mode switch direction register data bus port latch carrier wave output carrier wave output valid bit direction register port latch direction register port latch data bus data bus direction register port latch data bus direction register port latch data bus http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 19 of 59 rej03b0140-0106 7545 group termination of unused pins 1. termination of common pins i/o ports: select an input port or an output port and follow each processing method. output ports: open. input ports: if the input level become unstable, through current flow to an input circuit, and the power supply current may increase. especially, when expe cting low consumption current (at stp or wit instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). we recommend processing unused pins through a resistor which can secure i oh (avg) or i ol (avg). table 8 termination of unused pins pin termination 1 (recommend) termination 2 (recommend) p0 0 /key 0 ? p0 7 /key 7 i/o port when selecting key-on wakeup functi on, perform termination of input port. p1 0 ? p1 1 (rlss-only pin) when selecting n-channel open-drain for output structure, open. p2 0 (led 0 )/int 0 when selecting n-channel open-drain for output structure, connect to v ss through a resistor. or set its port latch to ?0? and open. p2 1 (led 1 )/int 1 when selecting n-channel open-drain for output structure, connect to v ss through a resistor. or set its port latch to ?0? and open. p2 2 (led 2 ) ? p2 7 (led 7 ) when selecting n-channel open-drain for output structure, open. p3 0 ? p3 7 when selecting n-channel open-drain for output structure, open. p4 0 (led 8 ) (rlss-only pin) ? p4 1 (led 9 ) (rlss-only pin) ? p4 2 /carr when selecting carr output function, perform termination of output port. v ddr connect to v ss . ? http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 20 of 59 rej03b0140-0106 7545 group interrupts the 7545 group interrupts are vector interrupts with a fixed priority scheme, and generate d by 7 sources 3 external, 3 internal, and 1 software. the interrupt sources, vector addresses (1) , and interrupt priority are shown in table 9. each interrupt except the brk instruction interrupt has the interrupt request bit and the interr upt enable bit. these bits and the interrupt disable flag (i flag) control the acceptance of interrupt requests. figu re 16 shows an interrupt control diagram. an interrupt requests is accept ed when all of the following conditions are satisfied: ? interrupt disable flag ................................ ?0? ? interrupt request bit .................................. ?1? ? interrupt enable bit ................................... ?1? though the interrupt priority is determined by hardware, priority processing can be performed by software using the above bits and flag. notes: 1. vector addressed contain interrupt jump destination addresses. 2. reset function in the same way as an interrupt with the highest priority. table 9 interrupt vector address and priority interrupt source priority vector addresses (1) interrupt request generating conditions remarks high- order low- order reset (2) 1fffd 16 fffc 16 at reset input non-maskable key-on wakeup 2 fffb 16 fffa 16 and operation of input logic level of port p0 (input) external interrupt int 0 3 fff9 16 fff8 16 at detection of either rising or falling edge of int 0 input external interrupt (active edge selectable) int 1 4 fff7 16 fff6 16 at detection of either rising or falling edge of int 1 input external interrupt (active edge selectable) timer 2 5 fff5 16 fff4 16 at timer 2 underflow timer 3 6 fff3 16 fff2 16 at timer 3 underflow timer 1 7 fff1 16 fff0 16 at timer 1 underflow stp release timer underflow brk instruction 8 ffdd 16 ffdc 16 at brk instruction execution non-maskable software interrupt http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 21 of 59 rej03b0140-0106 7545 group fig. 16 interrupt control diagram ? interrupt disable flag the interrupt disable flag is as signed to bit 2 of the processor status register. this flag contro ls the acceptance of all interrupt requests except for the brk instruction. when this flag is set to ?1?, the acceptance of interrupt requests is disabled. when it is set to ?0?, acceptance of interrupt requests is enabled. this flag is set to ?1? with the set instruction and set to ?0? with the cli instruction. when an interrupt request is accepted, the contents of the processor status register are pu shed onto the stack while the interrupt disable flag remains set to ?0?. subsequently, this flag is automatically set to ?1? and multiple interrupts are disabled. to use multiple interrupts, set this flag to ?0? with the cli instruction within the inte rrupt processing routine. the contents of the processor stat us register are popped off the stack with the rti instruction. ? interrupt request bits once an interrupt request is generate d, the corresponding interrupt request bit is set to ?1? and remains ?1? until the request is accepted. when the request is accepted, this bit is automatically set to ?0?. each interrupt request bit can be set to ?0?, but cannot be set to ?1?, by software. ? interrupt enable bits the interrupt enable bits control the acceptance of the corresponding interrupt requests. wh en an interrupt enable bit is set to ?0?, the acceptance of th e corresponding interrupt request is disabled. if an interrupt reque st occurs in this condition, the corresponding interrupt request bit is set to ?1?, but the interrupt request is not accepted. when an in terrupt enable bit is set to ?1?, acceptance of the corresponding interrupt request is enabled. each interrupt enable bit can be set to ?0? or ?1? by software. the interrupt enable bit for an unused interrupt should be set to ?0?. ? interrupt edge selection the valid edge of external interrupt int 0 and int 1 can be selected by the interrupt edge selection register(address003a 16 ), respectively. ? key-on wakeup pin selection by setting the key-on wakeup pin selection register (address 0018 16 ), the valid or invalid of key-on wakeup for each pin can be selected. ? key-on wakeup edge selection by setting the key-on wakeup ed ge selection register (address 0019 16 ), the trigger edge of key-on wakeup for each pin can be selected. interrupt disable flag i interrupt request interrupt request bit interrupt enable bit brk instruction reset http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 22 of 59 rej03b0140-0106 7545 group fig. 17 structure of interrupt-related registers b7 interrupt request register 1 (ireq1 : address 003c 16 , initial value : 00 16 ) timer 2 interrupt request bit key-on wakeup interrupt request bit timer 1 interrupt request bit timer 3 interrupt request bit int 1 interrupt request bit int 0 interrupt request bit disable (returns ?0? when read) (do not write ?1? to these bits) b0 b7 b0 interrupt edge selection register int 0 interrupt edge selection bit (intedge : address 003a 16 , initial value : 00 16 ) disable (returns ?0? when read) 1 : rising edge active 0 : falling edge active int 1 interrupt edge selection bit 1 : rising edge active 0 : falling edge active port p0 4 port p0 1 port p0 0 0: key-on wakeup invalid 1: key-on wakeup valid b7 b0 port p0 2 port p0 3 port p0 5 port p0 6 port p0 7 key-on wakeup pin selection register (keysel: address 0018 16 , initial value: 00 16 ) b7 b0 port p0 4 port p0 1 port p0 0 0: falling edge 1: rising edge port p0 2 port p0 3 port p0 5 port p0 6 port p0 7 key-on wakeup edge selection register (keyedge: address 0019 16 , initial value: 00 16 ) timer 2 interrupt enable bit b7 interrupt control register 1 (icon1 : address 003e 16 , initial value : 00 16 ) key-on wakeup interrupt enable bit timer 1 interrupt enable bit timer 3 interrupt enable bit int 1 interrupt enable bit int 0 interrupt enable bit disable (returns ?0? when read) (do not write ?1? to these bits) b0 http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 23 of 59 rej03b0140-0106 7545 group ? interrupt request generati on, acceptance, and handling interrupts have the following three phases. (i) interrupt request generation an interrupt request is gene rated by an interrupt source (external interrupt signal input, timer underflow, etc.) and the corresponding request bit is set to ?1?. (ii) interrupt request acceptance based on the interrupt acceptance timing in each instruction cycle, the interrupt control circuit determines acceptance conditions (interrupt request b it, interrupt enable bit, and interrupt disable flag) and in terrupt priority levels for accepting interrupt requests. when two or more interrupt requests are generated simultan eously, the highest priority interrupt is accepted. the valu e of interrupt request bit for an unaccepted interrupt remains the same and acceptance is determined at the next inte rrupt acceptance timing point. (iii) handling of accept ed interrupt request the accepted interrupt request is processed. figure 18 shows the time up to execution in the interrupt processing routine, and figure 19 shows the interrupt sequence. figure 20 shows the timing of interrupt request generation, interrupt request bi t, and interrupt re quest acceptance. ? interrupt handling execution when interrupt handlin g is executed, the following operations are performed automatically. (1) once the currently executing instruction is completed, an interrupt request is accepted. (2) the contents of the program counters and the processor status register at this point are pushed onto the stack area in order from 1 to 3. 1. high-order bits of program counter (pc h ) 2. low-order bits of program counter (pc l ) 3. processor status register (ps) (3) concurrently with the push operation, the jump address of the corresponding interrupt (the start address of the interrupt processing routine) is transferred from the interrupt vector to the program counter. (4) the interrupt reque st bit for the corresponding interrupt is set to ?0?. also, the interrupt disable flag is set to ?1? and multiple interrupts are disabled. (5) the interrupt routine is executed. (6) when the rti instruction is executed, the contents of the registers pushed onto the stack area are popped off in the order from 3 to 1. then, the routine that was before running interrupt processing resumes. as described above, it is necess ary to set the stack pointer and the jump address in the vect or area corresponding to each interrupt to execute the interrupt processing routine. the interrupt request bit may be set to ?1? in the following cases. ? when setting the external interrupt active edge related registers: interrupt edge selection register (address 003a 16) key-on wakeup edge selection register (address 0019 16 ) if it is not necessary to generate an interrupt synchronized with these settings, take the following sequence. (1) set the corresponding enable bit to ?0? (disabled). (2) set the interrupt edge select ion bit (the acti ve edge switch bit) or the interrupt source bit. (3) set the corresponding interrupt request bit to ?0? after one or more instructions have been executed. (4) set the corresponding interrupt enable bit to ?1? (enabled). fig. 18 time up to execution in interrupt routine fig. 19 interrupt sequence 7 cycles interrupt request generated interrupt request acceptance interrupt routine starts interrupt sequence * 0 to 16 cycles 7 to 23 cycles * when executing div instruction main routine stack push and vector fetch interrupt handling routine sync rd wr push onto stack vector fetch address bus data bus execute interrupt routine pc s,sps s-1,sps s-2,sps b l b h a l ,a h not used pc h pc l ps a l a h sync : cpu operation code fetch cycle (this is an internal signal that can not be observed from the external unit.) bl, bh: vector address of each interrupt al, ah: jump destination address of each interrupt sps : ?00 16 ? or ?01 16 ? ([sps] is a page selected by the stack page selection bit of cpu mode register.) http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 24 of 59 rej03b0140-0106 7545 group fig. 20 timing of interrupt request generation, interrupt request bit, and interrupt acceptance t1 (1) the interrupt request bit for an interrupt request genera ted during period 1 is set to ?1? at timing point ir1. (2) the interrupt request bit for an interrupt request generated during period 2 is set to ?1? at timing point ir1 or ir2. the timing point at which the bit is set to ?1? varies depending on conditions. when two or more interrupt requests are generated during the period 2, each request bit may be set to ?1? at timing point ir1 or ir2 separately. t1 t2 t3 : interrupt acceptance timing points ir1 ir2 : timings points at which the interrupt request bit is set to ?1?. note : period 2 indicates the last cycle during one instruction cycle. ir1 t2 sync ir2 t3 12 internal clock instruction cycle push onto stack vector fetch instruction cycle http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 25 of 59 rej03b0140-0106 7545 group key input interrupt (key-on wake-up) a key-on wake-up interrupt request is generated by applying the level set by keyedge to any pin of port p0 that has been set to input mode and keysel has been valid. in other words, it is generated when the and of input level goes from ?1? to ?0? or from ?0? to ?1?. an example of using a key input interrupt is shown in figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports p0 0 to p0 3 as input ports. fig. 21 connection example when using key input interrupt and port p0 block diagram port pxx ?l? level output pull register bit 7 = ?0? port p0 7 latch port p0 7 direction register = "1? ** * p0 7 output key input interrupt request port p0 input read circuit * p-channel transistor for pull-up ** cmos output buffer pull register bit 6 = "0? port p0 6 latch port p0 6 direction register = "1? ** * p0 6 output pull register bit 5 = "0? port p0 5 latch port p0 5 direction register = "1? ** * p0 5 output pull register bit 4 = "0? port p0 4 latch port p0 4 direction register = "1? ** * p0 4 output pull register bit 3 = "1? port p0 3 latch port p0 3 direction register = "0? ** * p0 3 input pull register bit 2 = "1? port p0 2 latch port p0 2 direction register = "0? ** * p0 2 input pull register bit 1 = "1? port p0 1 latch port p0 1 direction register = "0? ** * p0 1 input pull register bit 0 = "1? port p0 0 latch port p0 0 direction register = "0? ** * p0 0 input falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection port p0 0 key-on wakeup selection register bit 0 port p0 1 key-on wakeup selection register bit 1 port p0 2 key-on wakeup selection register bit 2 port p0 3 key-on wakeup selection register bit 3 port p0 4 key-on wakeup selection register bit 4 port p0 5 key-on wakeup selection register bit 5 port p0 6 key-on wakeup selection register bit 6 port p0 7 key-on wakeup selection register bit 7 http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 26 of 59 rej03b0140-0106 7545 group timers the 7545 group has 3 timers: ti mer 1, timer 2 and timer 3. the division ratio of every ti mer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. all the timers are down count timers. when a timer reaches ?0?, an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. when a timer underflows, the interrupt request bit corresponding to each timer is set to ?1?. 1. timer 1 timer 1 is an 8-bit timer and counts the prescaler 1 output. when timer 1 underflows, the timer 1 interrupt request bit is set to ?1?. prescaler 1 is an 8-bit presca ler and counts the clock which is f(x in ) divided by 16. prescaler 1 and timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. the value of prescaler 1 latch is set to prescaler 1 when prescaler 1 underflows. the value of timer 1 latch is set to timer 1 when timer 1 underflows. when writing to prescaler 1 (pre1) is executed, the value is written to both the prescaler 1 latch and prescaler 1. when writing to timer 1 (t1) is executed, the value is written to both the timer 1 latch and timer 1. when reading from prescaler 1 (pre1) and timer 1 (t1) is executed, each count value is read out. timer 1 always operates in the timer mode. prescaler 1 counts the clock which is f(x in ) divided by 16. each time the count clock is input, th e contents of prescaler 1 is decremented by 1. when the c ontents of prescaler 1 reach ?00 16 ?, an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into prescaler 1 and count continues. the division ratio of prescaler 1 is 1/(n+1) provided that the value of prescaler 1 is n. timer 1 counts the underflow signa l of prescaler 1. the contents of timer 1 is decremented by 1 each time the count clock is input. when the contents of timer 1 reach ?00 16 ?, an underflow occurs at the next count clock, and the timer 1 latch is reloaded into timer 1 and count continues. the division ratio of timer 1 is 1/(m+1) provided that the value of timer 1 is m. timer 1 is stopped by setting ?1? to the timer 1 count stop bit. 2. timer 2 timer 2 is an 8-bit timer and counts the clock selected by the timer 2 count source selection bit. when timer 2 underflows, the timer 2 interrupt request bit is set to ?1?. timer 2 has two timer latches (primary latch and secondary latch) to retain the reload value. the value written to timer 2 primary (t2p) while timer 2 is stopped is transferred to the timer 2 primary latch and the counter. the value written to timer 2 s econdary (t2s) while timer 2 is stopped is transferred only to timer 2 secondary latch. after the count of timer 2 starts, the values written to timer 2 primary (t2p) and timer 2 second ary (t2s) are tr ansferred only to each latch. the values are not transferred to the counter at write. when each timer underflows, the va lues of timer 2 primary latch and the timer 2 secondary latch ar e alternately transferred to the counter. (since a count value of a timer is retained, the written value becomes the count value of the timer after the next underflow.) when timer 2 primary (t2p) is re ad, the count value of the timer is read. when timer 2 secondary (t2s) is read, a set value of timer 2 secondary is read. (read the timer 2 primar y to read the count value even during the coun t period of timer 2 secondary.) when the timer 2 primary is r ead, the count value of timer 2 is read since the count value of the timer 2 is retained until writing to timer 2 primary (t2p) is pe rformed after timer 2 is stopped. timer 2 always operates in the timer mode. timer 2 counts the clock select ed by the timer 2 count source selection bit. the contents of timer 2 is decremented by 1 each time the count clock is input. when the contents of timer 2 reach ?00 16 ?, an underflow occurs at the next count clock, and the timer 2 primary latch or timer 2 secondary latch is alternately reloaded into timer 2 and count continues. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 27 of 59 rej03b0140-0106 7545 group 3. timer 3 timer 3 is an 8-bit timer and counts the clock selected by the timer 3 count source selection bit. when timer 3 underflows, the timer 3 interrupt request bit is set to ?1?. timer 3 has a timer latch to retain the reload value. the value written to timer 3 (t3) while timer 3 is stopped is transferred to the time r latch and the counter. after the count of timer 3 (t3) starts, the value written to timer 3 is transferred only to the timer 3 latch. the value is not transferred to the counter at write. when timer underflows, the value of timer 3 latch is transferred to the counter. (since a count value of a timer is retained, the written value becomes the count value of the timer after the next underflow.) when timer 3 (t3) is read, the c ount value of the timer is read. when the timer 3 is read, the count value of timer 3 is read since the count value of the timer 3 is retained until writing to timer 3 (t3) is performed af ter timer 3 is stopped. timer 3 always operates in the timer mode. timer 3 counts the clock select ed by the timer 3 count source selection bit. the contents of timer 3 is decremented by 1 each time the count clock is input. the division ratio of timer 3 is 1/(n+1) provided that the value of timer 3 is n. timer 3 is stopped by setting ?1? to the timer 3 count stop bit. timer 2 and timer 3 are also used for the control timer of the carrier wave control circuit. fig. 22 structure of timer count source set register fig. 23 timer 1, 2, 3 control register b7 b0 timer count source set register (tcss : address 002a 16 , initial value: 00 16 ) timer 2 count source selection bits b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in )/8 1 1 : f(x in )/1 disable (return ?0? when read) timer 3 count source selection bits b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in )/8 1 1 : carrier wave output (carry) b7 timer 1, 2, 3 control register (tc123 : address 002b 16 , initial value: 06 16 ) timer 1 count stop bit 0: count start 1: count stop timer 2 count stop bit 0: count start 1: count stop timer 3 count stop bit 0: count start 1: count stop disable (return ?0? when read) b0 http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 28 of 59 rej03b0140-0106 7545 group . fig. 24 block diagram of timer 1, timer 2, timer 3 and carrier wave generating circuit 1/16 1/2 1/8 1/1 timer 2 secondary latch (8) timer 2(8) wave expansion function reload control circuit reload control circuit timer 2 primary latch (8) timer 2 interrupt reque st timer 3 interrupt reques t timer 3 count value reload bit p4 2 /carr "00" "0" "1" "0" "0" "1" "01" "10" "11" timer 1(8) prescaler 1 (8) timer 3 latch (8) carrier wave output valid bit software carrier wave output bit carrier wave output level bit timer 3(8) timer 1 latch (8) prescaler 1 latch (8) timer 1 interrupt reque st f(x in )/16 t imer 2 count source selection bits 1/16 1/2 1/8 "00" "01" "10" "11" timer 3 count source selection bits toggle flip flop toggle flip flop timer 2 count value reload bit t r q t r q carrier wave "h" interval expansion bit trigger stop carrier wave output trigger bit data bus data bus data bus "1" "0" carrier wave auto-output control bit "1" http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 29 of 59 rej03b0140-0106 7545 group 4. carrier wave generating circuit the carrier wave generating circuit is used to generate the control wave of the remote control by using timer 2 and timer 3 (figure 26). in order to use the carrier wa ve generating function by timer 2, set ?1? to the carrier wave output valid bit (bit 1 of the carrier wave control register (address 27 16 )). carrier wave ?h? duration is set to the timer 2 primary, and carrier wave ?l? duration is set to the timer 2 secondary. timer 2 counts a primary latch and a sec ondary latch alternately, and controls carrier wave ?h? dura tion and the ?l? duration (figure 27). the ?h? duration of the carrier waveform can be expanded for a half clock of timer 2 count sour ce by setting ?1? to the carrier wave ?h? duration bit (bit 0) (figure 28). therefore, the frequency of the carrier wave can be set by the resolution of 1/2 of the timer 2 count source. for example, the carrier wave of the resolution of 125 ns (max.) can be generated at f(x in) = 4 mhz when f(x in )/1 is selected for the timer 2 count source. in order to initialize the carrier waveform, write in the timer 2 primary after stopping the count of timer 2, and then, start the count of timer 2 . the output of the carrier waveform is started from a primary period. output/stop of the carrier waveform can be controlled by software or timer 3 (figure 31 and figure 32). the output of the carrier wave is started from the p4 2 /carr pin when ?1? is set to the software carrier wave output bit (bit 2), and the output of the carrier wave is stopped when ?0? is written. the auto-output of the carrier wave using timer 3 can be performed by setting ?1? to the ca rrier wave auto-output control bit (bit 3) (figure 29). each time timer 3 underflow occurs, the trigger signal which is used to turn the output of the carrier wave on/off is generated. the trigger from timer 3 becomes valid by setting ?1? to the carrier wave output trigger bit (b it 4), and the output/stop of the carrier wave from the p4 2 /carr pin is repeated each time timer 3 underflows. timer 3 count cont inues without stopping though the output/stop state of the carrier wave at that time is maintained when ?0? is written to the carrier wave auto-output control bit (bit 3) while the output of th e carrier wave by timer 3 is controlled. in order to initialize output/stop control of the carrier waveform, write in the timer 3 after stopping the count of timer 3, and then, start the count of timer 3. the output of the carrier waveform is started from ?waveform output valid period?. 5. 455 khz carrier wave generating mode the 455 khz carrier wave generati ng mode is used to generate artificially the 455 khz carrier wave by auto-control of the setting value of the timer, or the waveform expansion mode. if ?1? (valid) is set to the 455 khz carrier wave generating mode bit (bit 5), the values of the timer latch and the carrier wave ?h? duration expansion bit (bit 0) are automatically set. then, the nine waveforms of 2.250 s wavelength and the seven waveforms of 2.125 s wavelength are generated periodically as shown in figure 30. the carrier wave of 455.516 khz can be pseudo generated since the average wavelength for one period becomes 2.195 s. in order to use 455 khz carrier wave generating mode, use the 4 mhz oscillator and select f(x in )/1 for the timer 2 count source. fig. 25 carrier wave control register b7 b0 carrier wave control register (carcnt : address 0027 16 , initial value: 00 16 ) carrier wave ?h? duration expansion bit 0: ?h? duration expansion function invalid 1: ?h? duration expansion function valid disable (return ?0? when read) carrier wave output valid bit 0: carrier wave generating function invalid 1: carrier wave generating function valid software carrier wave output bit 0: output invalid 1: output valid carrier wave auto-output control bit 0: auto-control by timer 3 invalid 1: auto-control by timer 3 valid carrier wave output trigger bit 0: carrier wave output trigger invalid 1: carrier wave output trigger valid 455 khz carrier wave generating mode bit 0: 455 khz carrier wave generating mode invalid 1: 455 khz carrier wave generating mode valid carrier wave output level bit 0: positive waveform 1: inverted waveform http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 30 of 59 rej03b0140-0106 7545 group fig. 26 operating waveform diagram of carrier wave generating circuit fig. 27 control waveform diagra m of carrier wave by timer 2 fig. 28 waveform diagram of carrier wave in ?h? duration expansion mode 04 carrier waveform control by timer 2 timer 2 count source timer 2 interrupt timer 2 count value carrier waveform primary timer 3 count source (carrier wave output selected) timer 3 interrupt timer 3 count value carrier waveform count period secondary secondary secondary primary primary primary 03 02 01 00 05 04 03 02 01 00 04 03 02 01 00 05 04 03 02 01 00 04 03 02 01 00 05 04 03 02 01 00 04 03 02 01 04 03 02 01 00 05 04 03 02 01 00 05 04 03 02 01 00 05 04 03 02 01 00 05 04 03 02 01 00 05 04 03 02 01 00 05 05 p4 2 /carr pin output the timing adjustment of the output waveform causes the gap between the timer count value and the output waveform, and the output waveform changes in the reload cycle after the timer underflow. moreover, the timer interrupt occurs at the change point of the output waveform. (the timing of the interrupt occurrence is behind a half cycle of the count source, compared with timer 1. ) note: carrier waveform control by timer 3 the timing adjustment of the output waveform causes the gap between the timer count value and the output waveform, and the output waveform changes in the reload cycle after the timer underflow. moreover, the timer interrupt occurs at the change point of the output waveform. (the timing of the interrupt occurrence is behind a half cycle of the count source, compared with timer 1. ) note: 04 03 02 01 00 05 04 03 02 01 00 05 04 03 02 01 00 04 03 02 01 00 05 04 03 02 01 00 04 03 02 01 00 05 04 03 02 0 1 t imer 2 count value writing to timer 2 secondary in this duration writing to timer 2 primary in this duration count value of primary side is changed count value of secondary side is changed primary secondary secondary secondary primary primary primary timer 2 count source timer 2 interrupt carrier waveform 03 02 01 00 04 03 02 01 00 03 02 01 04 00 03 02 01 00 t imer 2 count source t imer 2 interrupt t imer 2 count value c arrier waveform primary secondary primary expansion duration for half-clock carrier wave ??duration expansion = invalid carrier wave ??duration expansion = valid secondary http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 31 of 59 rej03b0140-0106 7545 group fig. 29 control waveform diagram of carr output by timer 3 fig. 30 waveform diagram in 455 khz carrier wave generating mode 06 05 04 03 02 01 00 02 01 00 03 03 01 00 03 02 02 00 01 02 01 00 03 02 01 00 03 03 01 00 03 02 02 00 01 02 0 1 03 p4 2 /carr pin output timer 3 count source (carrier wave output selected) timer 3 interrupt timer 3 count value count period generating carrier waveform or not is controlled by setting carrier waveform output trigger bit. c arrier waveform output trigger bit writing to timer 3 in this duration count value of next period is changed successive carrier waveform is not generated in this duration. 2.250 s x 9 waveforms + 2.125 s x 7 waveforms 2.125 s waveform duration (7 waveforms) 35.125 s (16 waveforms), average waveform = 2.195 s (frequency = 455.516 khz) waveform period in 455 khz carrier waveform generating mode waveform length: 2.250 s-waveform waveform length: 2.125 s-waveform 2.250 s 5-clock 4-clock 2.125 s 4.5-clock 4-clock c arrier waveform timer 2 count source carrier waveform timer 2 count source carrier waveform http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 32 of 59 rej03b0140-0106 7545 group fig. 31 setting of carrier wave auto-control by timer 3 carrier waveform (timer 2 output) timer 3 count value timer 3 underflow carrier wave output trigger bit p4 2 /carr pin output output valid output valid waveform output timing of remote-control waveform by carrier waveform output trigger bit 03 02 01 00 03 02 01 00 03 02 01 00 03 02 01 00 03 02 01 00 03 02 01 00 03 02 01 00 04 04 04 04 04 04 04 0xx0000x b7 b0 12 11 0000011x b7 b0 10 0xx0101x b7 b0 9 000011xx b7 b0 6 0000000x b7 b0 7 0xxx101x b7 b0 8 0000011x b7 b0 1 0000xxxx b7 b0 2 0xxx1 0 1x b7 b0 3 xxxxxxxx b7 b0 xxxxxxxx b7 b0 4 xxxxxxxx b7 b0 5 output invalid trigger invalid (successive output invalid duration) trigger invalid (successive output valid duration) start (initial state after reset) timer 1, 2, 3 control register tc123 (2b 16 ) set ??to bit 1 and bit 2 to stop counting of timer 2 and timer 3. timer count source set register tcss (2a 16 ) x: set it to ??or ??arbitrary. select carrier waveform output for timer 3 count source by bit 2 and bit 3. timer 1, 2, 3 control register tc123 (2b 16 ) set ??to bit 1 and bit 2 to start counting of timer 2 and timer 3. carrier wave control register, carcnt (27 16 ) during waveform output of remote-control, whether to output waveform or not can be controlled by ?it 4: carrier waveform output trigger bit? (refer to figure below.) carrier wave control register, carcnt (27 16 ) when waveform output is stopped, set ??to ?it 4: carrier waveform output trigger bit? while carrier waveform output is set to be invalid. timer 1, 2, 3 control register tc123 (2b 16 ) set ??to bit 1 and bit 2 to stop counting of timer 2 and timer 3. when the carrier wave output circuit operation is started again, execute the setting from the processing no.2. carrier wave control register, carcnt (27 16 ) in order to change the carrier wave control from the auto-control by timer 3 to software carrier wave output, initialize the carrier wave circuit by setting ??to ?it 1: carrier wave output valid bit? timer count source set register tcss (2a 16 ) set timer 2 count source to bit 0 and bit 1. also, in order to initialize carrier waveform circuit, be sure to select f(x in )/16, f(x in )/2 or f(x in )/8 for timer 3 count source. do not select carrier waveform output (b3b2=11 2 ) for timer 3 count source. carrier wave control register, carcnt (27 16 ) set carrier wave control register. bit 0: set whether to expand waveform. bit 1: select ?: carrier waveform generating function is valid? bit 2: select ?: software output is invalid bit 3: select ?: auto-control by timer 3 is valid. bit 4: select whether carrier waveform output trigger is valid or invalid. bit 5: select whether 455 khz carrier wave generating mode is valid or invalid. bit 6: set output level of waveform. bit 7: set this bit to ?? timer 2 secondary t2s (2d 16 ) timer 2 primary t2p (2c 16 ) set carrier wave ?? ??duration to timer 2 primary and timer 2 secondary, respectively.(when 455 khz carrier waveform generating mode is used, this setting is not necessary.) timer 3 t3 (2e 16 ) set valid period/invalid period of carrier waveform output to timer 3. waveform output of remote-control http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 33 of 59 rej03b0140-0106 7545 group fig. 32 setting of carrier wave control by software 0 x x 0 0x 1 x b7 b0 0 0 0 0 0 x1 x b7 b0 1 0 0 0 0 x x xx b7 b0 2 x x x x x x xx b7 b0 x x x x x x xx b7 b0 4 0 x x 0 0 0 1x b7 b0 3 0 0 0 0 0 x0 x b7 b0 5 6 9 0 x x 0 00 1 x b7 b0 7 0 0 0 0 0 x1 x b7 b0 8 0 x x 00 00 x b7 b0 10 p4 2 /carr pin output carrier waveform (timer 2 output) s oftware carrier wave output bit waveform output timing of remote-control waveform by software carrier waveform output bit set ??to bit 1 to stop counting of timer 2. timer 1, 2, 3 control register tc123 (2b 16 ) set ??to bit 1 to start counting of timer 2. carrier wave control register, carcnt (27 16 ) timer 1, 2, 3 control register tc123 (2b 16 ) set ??to bit 1 to stop counting of timer 2. carrier wave control register, carcnt (27 16 ) carrier wave control register, carcnt (27 16 ) timer count source set register tcss (2a 16 ) set timer 2 count source to bit 0 and bit 1. also, in order to initialize carrier waveform circuit, be sure to select f(x in )/16, f(x in )/2 or f(x in )/8 for timer 3 count source. do not select carrier waveform output (b3b2=11 2 ) for timer 3 count source. carrier wave control register, carcnt (27 16 ) timer 2 secondary t2s (2d 16 ) timer 2 primary t2p (2c 16 ) set carrier wave ?? ??duration to timer 2 primary and timer 2 secondary, respectively. (when 455 khz carrier waveform generating mode is used, this setting is not necessary.) waveform output of remote-control start (initial state after reset) timer 1, 2, 3 control register tc123 (2b 16 ) generating waveform or not can be controlled by bit 2: software carrier waveform output bit in order to stop carrier waveform, set bit 2: software carrier waveform output bit to ?: output invalid? x: set it to ??or ??arbitrary . when the carrier wave output circuit operation is started again, execute the setting from the processing no.4 . in order to change the carrier wave control from the auto-control by timer 3 to software carrier wave output, initialize the carrier wave circuit by setting ??to ?it 1: carrier wave output valid bit? set carrier wave control register. bit 0: set whether to expand waveform. bit 1: select ?: carrier waveform generating function is valid? bit 2: select ?: software output is invalid bit 3: select ?: auto-control by timer 3 is invalid. bit 4: select ?: carrier waveform output trigger is invalid bit 5: select whether 455 khz carrier waveform generating mode is valid or invalid. bit 6: set output level of waveform. bit 7: set this bit to ?? http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 34 of 59 rej03b0140-0106 7545 group watchdog timer the watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. the watchdog timer consists of an 8-bit watchdog timer h and an 8-bit watchdog timer l, being a 16-bit counter. 1. standard operation of watchdog timer the watchdog timer is valid by setting ?0? to bit 0 of the function set rom data (address ffda 16 ) of the built-in qzrom. when an internal clock is supp lied after waiting the oscillation stabilizing time by timer 1 after system is released from reset, the watchdog timer starts operatio n. when the watchdog timer h underflows, an internal rese t occurs. accordingly, it is programmed that the watchdog ti mer control register (address 0039 16 ) can be set before an underflow occurs. when the watchdog timer control register (address 0039 16 ) is read, the values of the high-order 6-bit of the watchdog timer h and watchdog timer h count sour ce selection bit are read. 2. initial value of watchdog timer by a reset or writing to the watchdog timer control register (address 0039 16 ), the watchdog timer h is set to ?ff 16 ? and the watchdog timer l is set to ?ff 16 ?. 3. operation of watchdog timer h count source selection bit a watchdog timer h count source ca n be selected by bit 7 of the watchdog timer c ontrol register (address 0039 16 ). when this bit is ?0?, the count source become s a watchdog timer l underflow signal. the detection ti me is 262.144 ms at f(x in ) = 4 mhz. when this bit is ?1?, the count source becomes f(x in )/16. in this case, the detect ion time is 1024 s at f(x in ) = 4 mhz. this bit is cleared to ?0? after reset. 4. stp instruction function selection bit the function of the stp instructio n can be selected by the bit 1 in fsrom. this bit cannot be used for rewriting by executing the stp instruction. ? when this bit is set to ?0?, internal reset occurs by executing the stp instruction. ? when this bit is set to ?1?, stop mode is entered by executing the stp instruction. 1. the watchdog timer is opera ting during the wait mode. write data to the watchdog timer control register to prevent timer underflow. 2. the watchdog timer stops durin g the stop mode. however, the watchdog timer is runnin g during the oscillation stabi- lizing time after the stp instru ction is released. in order to avoid the underflow of the watchdog timer, the watchdog timer h count source selection bit (bit 7 of watchdog timer control register (address 0039 16 )) must be set to ?0? just before executing the stp instruction. fig. 33 structure of watc hdog timer control register b7 b0 watchdog timer h (read only for high-order 6-bit) watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 watchdog timer control register (wdtcon: address 0039 16 , initial value: 3f 16 ) disable (returns ?0? when read) http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 35 of 59 rej03b0140-0106 7545 group fig. 34 timing diagram at reset fig. 35 block diagram of watchdog timer and reset circuit f (x in ) f(x in ) 16384 pulses r eset i nternal reset signal c pu clock ? ? ?fff cfffd ? ? ? ? adl adh ? adh, adl s ync d ata a ddress write "ff 16 " to the watchdog timer control register x in watchdog timer h count source selection bit "0" "1" watchdog timer h(8) reset circuit watchdog timer l(8) voltage drop detection circuit power-on reset circuit internal reset 1/16 s tp instuction function selection bit stp instruction reset write "ff 16 " to the watchdog timer control register count start (watchdog timer disable bit (bit 0 of fsrom) http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 36 of 59 rej03b0140-0106 7545 group power-on reset circuit reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. in order to use the power-on reset circuit effectively, the time for the supply voltage to rise from 0 v to 1.8 v must be set to 1 ms or less. voltage drop detection circuit the built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value (typ.1.75 v). when the stp instruction is executed, the vo ltage drop detection circuit is stopped, so that the power dissipation is reduced. the operation of the voltage drop de tection circuit is disabled by setting ?0? to bit 4 of the fu nction set rom data (address ffda 16 ) of the built-in qzrom. note: the emulator mcu ?m37545rlss? is not equipped with the voltage drop detection circuit. resetout output resetout function is used to output ?l? level from reset pin when system reset occurs by the power-on reset, the voltage drop detection circuit or the watchdog timer. also, the built-in pull-up transistor is connected to the reset pin. fig. 36 operation waveform diagram of power-on reset circuit fig. 37 operation waveform diagra m of voltage drop detection circuit the voltage drop detection circ uit detection voltage of this product is set up lower than th e minimum value of the supply voltage of the recomme nded operating conditions. when the supply voltage of a mic rocomputer falls below to the minimum value of recommende d operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the fo llowing case may cause program failure ; supply voltage does not fall below to v det , and its voltage re- goes up with no reset. in such a case, please design a system which supply voltage is once reduced below to v det and re-goes up after that. fig. 38 v cc and v det v cc (note ) 1 ms or les s power-on reset released internal reset signal reset state n ote: keep the value of supply voltage to the minimum valu e or more of the recommended operating conditions. po circuit output wer-on reset v cc i nternal reset signal r eset voltage (typ:1.75v) microcomputer starts operation after f(x in ) clock is counted 16384 times. note: the voltage drop detection circuit does not have the hysteresis characteristics in the detected voltag e. vcc v det reset normal operation no reset program failure may occur. recommended o perating condition min. value vcc v det recommended o perating condition min. value http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 37 of 59 rej03b0140-0106 7545 group misrg the 7545 group has two power sour ce supply pins. one is the v cc pin, and the other is the v ddr pin only for ram2. a potential difference between v cc and v ddr may cause some failures in reading from ram2 or writing to ram2. accordingly, if there is a potential difference between v cc and v ddr at power-on, confirm the bit 1 (ram2 status flag) of misrg (address 0038 16 ) before reading from ram2 or writing to ram2. fig. 39 structure of misrg fig. 40 internal status of microcomputer at reset b7 b0 ram2 status flag 0: rw disabled 1: rw enabled oscillation stabilizati on time set bit after release of the stp instruction 0: set ?03 16? in timer1, and ?ff 16? in prescaler 1 automatically 1: not set automatically reserved bits (do not write ?1? to these bits) misrg(address 0038 16 , initial value: 0x 16 ) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16)( 17) (18) (19) (20) (21) (22) (23) (24) (25) 0001 16 0003 16 0005 16 0007 16 0009 16 0016 16 0017 16 0018 16 0019 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 0038 16 0039 16 003a 16 003b 16 003c 16 003e 16 (ps) (pch) (pcl) 00 16 00 00 16 00 16 00 16 00 16 00 16 ff 16 03 16 00 16 06 16 ff 16 ff 16 000000 0 00111111 10000000 00 16 00 16 x1 00 16 00 16 000 ff 16 00000000 register contents address port p0 direction register (p0d) port p1 direction register (p1d) port p2 direction register (p2d) port p3 direction register (p3d) port p4 direction register (p4d) pull-up control register (pull) port output mode switch register (pmod) key-on wakeup pin selection register (keysel) key-on wakeup edge select ion register (keyedge) carrier wave control register (carcnt) prescaler 1 (pre1) timer 1 (t1) timer count source set register (tcss) timer 1, 2, 3 control register (tc123) timer 2 primary (t2p) timer 2 secondary (t2s) timer 3 (t3) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) processor status register program counter contents of address fffd 16 contents of address fffc 16 xxxx xx x xx xx xx x xx xx x : undefined the content of other registers and ram are undefined when the microcomputer is reset. the initial values must be surely set before you use it. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 38 of 59 rej03b0140-0106 7545 group clock generating circuit an oscillation circuit can be fo rmed by connecting a resonator between x in and x out . use the circuit constants in accordance with the resonator manufacturer's re commended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip . (an external feed-back resistor may be needed depe nding on conditions.) when the ceramic resonator/quartz- crystal oscillator is used for the main clock, connect the cer amic resonator/quartz-crystal oscillator and the external circuit to pins x in and x out at the shortest distance. a feedback resi stor is built in between pins x in and x out . (an external feed-back resistor may be needed depending on conditions.) oscillation control 1. stop mode when the stp instruction is executed, the internal clock stops at an ?h? level and the x in oscillator stops. at this time, timer 1 is set to ?03 16 ? and prescaler 1 is set to ?ff 16 ?when the oscillation stabilization time set bit after release of the stp instruction is ?0?. on the other hand, timer 1 and prescaler 1 are not set when the above bit is ?1?. accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. when an external interr upt is accepted, oscillation is restarted but the internal clock remains at ?h? until timer 1 underflows. as soon as timer 1 underflows, the internal clock is supplied. this is because when a ceramic resonator is used, some time is required until a start of oscillation. in the stop mode, the voltage drop detection circuit is stopped, so that the power diss ipation is reduced. 2. wait mode if the wit instruction is executed, the internal clock stops at an ?h? level, but the oscillator does not stop. the internal clock restarts if a reset occurs or when an interrupt is accepted. since the oscillator does not stop, normal operati on can be started immediately after the clock is restarted. to ensure that an interrupt will be accepted to release the stp or wit state, the corresponding interrupt enable bit must be set to ?1? before the stp or wit instruction is executed. fig. 41 external circuit of ceramic resonator/quartz-crystal oscillator fig. 42 structure of cpu mode register x in x out c in c out rd m37545 note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. also, if the oscillator manufacturer?s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between x in and x out following the instruction. processor mode bits (note) b1 b0 0 0 single-chip mode 01 10 11 not available b7 b0 note : the bit can be rewritten only once after releasing reset. after rewriting, it is disabled to write any data to this bit. however, by reset the bit is initialized and can be rewritten, again. it is not disabled to write any data to this bit for emulator mcu ?gm37545rlss .?h cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0:0page 1:1page clock division ratio selection bits b7 b6 0 0 : not available 0 1 : not available 10:f( ) = f(x in )/4 1 1 : not available not used (returns ?g0?h when read) http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 39 of 59 rej03b0140-0106 7545 group fig. 43 block diagram of system clock gen erating circuit (for ceramic resonator) s r q s r q 1/2 x in r s q interrupt request interrupt disable flag i reset stp instruction timing (internal clock) prescaler 1 timer 1 rf stp instruction wit instruction 1/2 1/4 reset although a feed-back resistor exists on -chip, an external feed-back resistor may be needed depending on conditions. note: x out http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 40 of 59 rej03b0140-0106 7545 group qzrom writing mode in the qzrom writing mode , the user rom area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is app licable for this microcomputer. table 10 lists the pin descript ion (qzrom writing mode) and figure 44 and figure 45 show the pin connections. refer to figure 46 and figure 47 for examples of a connection with a serial programmer. contact the manufacturer of y our serial programmer for serial programmer. refer to the user?s manual of your serial programmer for details on how to use it. table 10 pin description (qzrom writing mode) pin name i/o function v cc , v ss , v ddr power source input ? apply 1.8 to 3.6 v to v cc , and 0 v to v ss and v ddr . reset reset input input ? reset input pin for active ? l ? . reset occurs when reset pin is hold at an ? l ? level for 16 cycles or more of x in . x in clock input input ? set the same term ination as the single-chip mode. x out clock output output p0 0 ? p0 5 p2 1 ? p2 7 p3 0 ? p3 7 p4 2 i/o port i/o ? input ? h ? or ? l ? level signal or leave the pin open. cnv ss v pp input input ? qzrom programmable power source pin. p0 7 esda input/output i/o ? serial data i/o pin. p2 0 esclk input input ? serial clock input pin. p0 6 espgmb input input ? read/program pulse input pin. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 41 of 59 rej03b0140-0106 7545 group fig. 44 pin connection diagram (m37545gx-xxxgp) fig. 45 pin connection diagram (m37545gxkp) package type: plqp0032gb-a (32p6u-a) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 8 7 6 5 3 4 v cc cnv ss p2 5 (led 5 ) p0 3 /key 3 p0 0 /key 0 p0 2 /key 2 p0 1 /key 1 p0 4 /key 4 p3 7 p3 6 p3 5 m37545gx-xxxgp m37545gxgp p2 6 (led 6 ) p2 7 (led 7 ) p4 2 /carr v ddr reset 12 p2 3 (led 3 ) p2 4 (led 4 ) p2 2 (led 2 ) p2 1 (led 1 )/int 1 p2 0 (led 0 )/int 0 p0 7 /key 7 p0 6 /key 6 p0 5 /key 5 x out x in v ss p3 0 p3 1 p3 2 p3 3 p3 4 24 23 22 21 20 19 18 17 esclk espgmb esda : connect to oscillation circuit : qzrom pin * * v cc v pp reset v ss package type: plsp0032jb-a p2 1 (led 1 )/int 1 32 m37545gxkp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p4 2 /carr reset v cc x in x out v ss p3 0 p2 0 (led 0 )/int 0 p0 7 /key 7 p0 6 /key 6 p0 5 /key 5 p0 4 /key 4 p0 3 /key 3 p0 2 /key 2 p0 1 /key 1 p3 7 p0 0 /key 0 p3 5 p3 4 p3 3 p3 2 p3 1 p3 6 cnv ss v ddr esda esclk espgmb v cc v pp v ss * : connect to oscillation circuit : qzrom pin * reset http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 42 of 59 rej03b0140-0106 7545 group fig. 46 when using e8 programmer, connection example 7545 group set the same termination as the single-chip mode. vcc cnv ss p0 7 (esda) p2 0 (esclk) p0 6 (espgmb) reset vss x in x out 4.7 k ? 4.7 k ? note: for the programming circuit, the wiring capaci ty of each signal pin must not exceed 47 pf. 13 11 9 7 5 3 1 14 12 10 8 6 4 2 reset circuit vcc * 1: open-collector buffer * 1 http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 43 of 59 rej03b0140-0106 7545 group fig. 47 when using programmer of suisei electronics system co., ltd, connection example 7545 group t_vdd t_vpp t_rxd t_sclk t_pgm/oe/md t_reset gnd reset circuit set the same termination as the single-chip mode. vcc cnv ss p0 7 (esda) p2 0 (esclk) p0 6 (espgmb) reset vss x in x out 4.7 k ? 4.7 k ? note: for the programming circuit, the wiring capacity of each signal pin must not exceed 47 pf. t_txd t_busy n.c. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 44 of 59 rej03b0140-0106 7545 group notes on programming processor status register the contents of the processor status register (ps) after reset are undefined except for the interrupt disable flag i which is ?1?. after reset, initialize flags whic h affect program execution. in particular, it is essential to initialize the t flag and the d flag because of their effe ct on calculations. interrupts the contents of the interrupt request bit do not change even if the bbc or bbs instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. for executing the instruction for the changed contents, execute one instruc tion before executing the bbc or bbs instruction. decimal calculations ? for calculations in decimal not ation, set the de cimal mode flag d to ?1?, then execute the adc instruction or sbc instruction. in this case, execute sec instru ction, clc instruction or cld instruction after executing one instruction before the adc instruction or sbc instruction. ? in the decimal mode, the values of the n (negative), v (overflow) and z (zero) flags are invalid. ports the values of the port direction re gisters cannot be read. that is, it is impossible to use the lda instruction, memory operation instruction when the t flag is ?1?, addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructi ons such as clb and seb and read/modify/write inst ructions of direction registers for calculations such as ror. for setting direction registers, use the ldm instruction, sta instruction, etc. instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. the frequency of the internal clock is 4 times the x in cycle. cpu mode register the processor mode bits can be rewritten only once after releasing reset. however, after rewriting it is disable to write any value to the bit. (emulator mcu is excluded.) notes on hardware handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin). besides, connect the capacitor to as close as possi ble. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f to 0.1 f is recommended. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 45 of 59 rej03b0140-0106 7545 group notes on use countermeasures against noise 1. shortest wiring length (1) package select the smallest possible package to make the total wiring length short. the wiring length depends on a microcomputer package. use of a small package, for example qfp and not dip, makes the total wiring length short to re duce influence of noise. fig. 48 selection of packages (2) wiring for reset pin make the length of wiring whic h is connected to the reset pin as short as possible. especially , connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20mm). the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cause a program runaway. fig. 49 wiring for the reset pin (3) wiring for clock input/output pins ? make the length of wiring whic h is connected to clock i/o pins as short as possible. ? make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ? separate the v ss pattern only for oscillation from other v ss patterns. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. fig. 50 wiring for clock i/o pins (4) wiring to cnv ss pin connect cnv ss pin to a gnd pattern at the shortest distance. the gnd pattern is required to be as close as possible to the gnd supplied to v ss . in order to improve the noise reduction, to connect a 5 k ? resistor serially to the cnv ss pin - gnd line may be valid. as well as the above-mentioned, in this case, connect to a gnd pattern at the shortest distance. the gnd pattern is required to be as close as possible to the gnd supplied to v ss . the cnv ss pin of the qzrom is the power source input pin for the built-in qzrom. when pr ogramming in the built-in qzrom, the impedance of the cnv ss pin is low to allow the electric current for writing flow into the qzrom. because of this, noise can enter easily. if noise enters the cnv ss pin, abnormal instruction codes or data are read from the built-in qzrom, which may caus e a program runaway. fig. 51 wiring for the v pp pin of the qzprom dip sdip sop qfp reset reset circuit noise v ss v ss reset circuit v ss reset v ss n.g. o.k. noise x in x out v ss x in x out v ss n.g. o.k. about 5k ? v ss the shortest the shorte s t cnv ss /v pp (note) (note) n ote: this indicates pin. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 46 of 59 rej03b0140-0106 7545 group 2. connection of bypass capacitor (1) connection of bypass capacitor across v ss line and v cc line connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: ? connect a bypass capacitor across the v ss pin and the v cc pin at equal length. ? connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. ? use lines with a larger diameter than other signal lines for v ss line and v cc line. ? connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. fig. 52 bypass capacitor across the v ss line and the v cc line (2) connection of bypass capacitor across v ss line and v ddr line connect an approximately 0.1 f bypass capacitor across the v ss line and the v ddr line as follows: ? connect a bypass capacitor across the v ss pin and the v ddr pin at equal length. ? connect a bypass capacitor across the v ss pin and the v ddr pin with the shortest possible wiring. ? use lines with a larger diameter than other signal lines for v ss line and v ddr line. ? connect the power source wiring via a bypass capacitor to the v ss pin and the v ddr pin. fig. 53 bypass capacitor across the v ss line and the v ddr line v ss v cc v ss v cc n.g. o.k. v ss v ddr v ss v ddr n.g. o.k. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 47 of 59 rej03b0140-0106 7545 group 3. oscillator concerns so that the product obtains the stabilized operation clock on the user system and its condition, c ontact the resonator manufacturer and select the resonator and oscillation circ uit constants. be careful especially when range of voltage and temperature is wide. take care to prevent an oscillator that generates clocks for a microcomputer operation from bei ng affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. in the system using a microcom puter, there are signal lines for controlling motors, leds, and ther mal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) installing oscillator away from signal lines where potential levels change frequently install an oscillator and a conn ecting pattern of an oscillator away from signal lines where pote ntial levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. signal lines where potenti al levels change fre quently (such as the carr pin signal line) may affect other lines at signal rising edge or falling edge. if such line s cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. fig. 54 wiring for a large current signal line/writing of signal lines where potential levels change frequently (3) oscillator protection using v ss pattern as for a two-sided printed circuit board, print a v ss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the v ss pattern to the microcomputer v ss pin with the shortest possible wiring. besides, separate this v ss pattern from other v ss patterns. fig. 55 v ss pattern on the underside of an oscillator x in x out v ss m mutual inductance large current gnd x in x out v ss carr do not cross n.g. 1. keeping oscillator away from large current signal lines 2. installing oscillator away from signal lines where potential levels change frequently microcomputer x in x out v ss an example of v ss patterns on the underside of a printed circuit board oscillator wiring pattern example separate the v ss line for oscillation from other v ss lines http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 48 of 59 rej03b0140-0106 7545 group 4. setup for i/o ports setup i/o ports using hardware and software as follows: ? connect a resistor of 100 ? or more to an i/o port in series. ? as for an input port, read data several times by a program for checking whether input levels are equal or not. ? as for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. ? rewrite data to direction regi sters and pull-up control registers at fixed periods. fig. 56 setup for i/o ports 5. providing of watchdog timer function by software if a microcomputer runs away becau se of noise or others, it can be detected by a software wa tchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runa way detection by a hardware watchdog timer. the following shows an example of a watchdog timer provided by software. in the following example, to reset a microcomputer to normal operation, the main routine de tects errors of the interrupt processing routine an d the interrupt processing routine detects errors of the main routine. this example assumes that in terrupt processing is repeated multiple times in a single main routine processing. ? assigns a single byte of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main rou tine. the initial value n should satisfy the following condition: n+1 (counts of interrupt proce ssing executed in each main routine) as the main routine execution cycle may change because of an interrupt processing or others, th e initial value n should have a margin. ? watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing after the initia l value n has been set. ? detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents do not cha nge after interrupt processing. ? decrements the swdt conten ts by 1 at each interrupt processing. ? determines that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed in terrupt processing count). ? detects that the main routine has failed and determines to branch to the program initia lization routine for recovery processing in the following case: if the swdt contents are not initialized to the initial value n but continued to decrement and if they reach 0 or less. fig. 57 watchdog timer by software direction register port latch data bus i/o port pins noise noise n.g. o.k. main routine (swdt) n cli main processing (swdt) interrupt processing routine errors n interrupt processing routine (swdt) (swdt) ? 1 interrupt processing (swdt) main routine errors > 0 0 rti return =n? 0? n http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 49 of 59 rej03b0140-0106 7545 group electrical characteristics (qzrom version) absolute maximum ratings table 11 absolute maximum ratings symbol parameter conditions ratings unit v cc power source voltage v cc , v ddr all voltages are based on v ss . when an input voltage is measured, output transistors are cut off. ? 0.3 to 5.0 v v i input voltage p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 2 ? 0.3 to v cc + 0.3 v v i input voltage reset , x in ? 0.3 to v cc + 0.3 v v i input voltage cnv ss ? 0.3 to v cc + 0.3 v v o output voltage p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 2 , x out , reset ? 0.3 to v cc + 0.3 v p d power dissipation ta = 25 c 200 mw t opr operating temperature ? 20 to 85 c t stg storage temperature ? 40 to 125 c http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 50 of 59 rej03b0140-0106 7545 group recommended operating conditions notes: 1. the total output current is the sum of all the currents flow ing through all the applicable ports. the total average current i s an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2. the peak output current is the peak current flowing in each port. 3. the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 4. when the oscillation frequency has a duty cycle of 50 %. table 12 recommended operating conditions (1) (v cc = 1.8 to 3.6 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. v cc power source voltage (at 4mhz) 1.8 3.0 3.6 v v ss power source voltage 0v v ih ? h ? input voltage p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 2 0.7v cc v cc v v ih ? h ? input voltage reset , x in 0.8v cc v cc v v il ? l ? input voltage p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 2 00.3v cc v v il ? l ? input voltage reset , cnv ss 00.2v cc v v il ? l ? input voltage x in 0 0.16v cc v i oh (peak) ? h ? total peak output current (1) p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 2 ? 80 ma i ol (peak) ? l ? total peak output current (1) p0 0 ? p0 7 , p1 0 ? p1 1 , p3 0 ? p3 7 80 ma i ol (peak) ? l ? total peak output current (1) p2 0 ? p2 7 , p4 0 ? p4 2 80 ma i oh (avg) ? h ? total average output current (1) p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 2 ? 40 ma i ol (avg) ? l ? total average output current (1) p0 0 ? p0 7 , p1 0 ? p1 1 , p3 0 ? p3 7 40 ma i ol (avg) ? l ? total average output current (1) p2 0 ? p2 7 , p4 0 ? p4 2 40 ma i oh (peak) ? h ? peak output current (2) p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 1 v cc = 3.0 v ? 4ma i oh (peak) ? h ? peak output current (2) p4 2 v cc = 3.0 v ? 20 ma i ol (peak) ? l ? peak output current (2) p0 0 ? p0 7 , p1 0 ? p1 1 , p3 0 ? p3 7 v cc = 3.0 v 4 ma i ol (peak) ? l ? peak output current (2) p2 0 ? p2 7 , p4 0 ? p4 2 v cc = 3.0 v 24 ma i oh (avg) ? h ? average output current (3) p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 1 v cc = 3.0 v ? 2ma i oh (avg) ? h ? average output current (3) p4 2 v cc = 3.0 v ? 10 ma i ol (avg) ? l ? average output current (3) p0 0 ? p0 7 , p1 0 ? p1 1 , p3 0 ? p3 7 v cc = 3.0 v 2 ma i ol (avg) ? l ? average output current (3) p2 0 ? p2 7 , p4 0 ? p4 2 v cc = 3.0 v 12 ma f(x in ) internal clock oscillation frequency (4) at ceramic oscillation or external clock input v cc = 1.8 to 3.6 v 4 mhz v det detection voltage of voltage drop detection circuit ta = ? 20 to 85 c 1.65 1.75 1.85 v ta = 0 to 50 c 1.70 1.75 1.80 v t det low-voltage detection time of voltage drop detection circuit when detected voltage passes detection voltage at 50v/s 0.2 1.2 ms t pon power-on reset circuit valid supply voltage rising time v cc = 0 to 1.8 v 1 ms http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 51 of 59 rej03b0140-0106 7545 group electrical characteristics notes: 1. in this case, cmos output is selected by the port output mode selection register. 2. it is available only when operating key-on wake up. table 13 electrical characteristics (1) (v cc = 1.8 to 3.6 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v oh ? h ? output voltage p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 (1) p4 0 ? p4 1 i oh = ? 2.0 ma v cc = 3.0 v 2.1 v v oh ? h ? output voltage p4 2 i oh = ? 10 ma v cc = 3.0 v 1.0 v v ol ? l ? output voltage p0 0 ? p0 7 , p1 0 ? p1 1 , p3 0 ? p3 7 i ol = 2 ma v cc = 3.0 v 0.9 v v ol ? l ? output voltage p2 0 ? p2 7 , p4 0 ? p4 2 i ol = 12 ma v cc = 3.0 v 1.5 v v t + ? v t -hysteresis int 0 , int 1 , p0 0 ? p0 7 (2) v cc = 3.0 v 0.3 v v t + ? v t -hysteresis reset v cc = 3.0 v 0.45 v i ih ? h ? input current p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 2 v i = v cc (pin floating. pull up transistors ? off ? ) 5.0 a i ih ? h ? input current reset v i = v cc 5.0 a i il ? l ? input current p0 0 ? p0 7 , p1 0 ? p1 1 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 2 v i = v ss (pin floating. pull up transistors ? off ?) ? 5.0 a r fb feed-back resistor value between x in -x out v cc = 3.0 v, v i = 3.0 v 700 3200 k ? r ph pull-up resistor value p0 0 ? p0 7 v cc = 3.0 v, v i = 0 v 50 120 250 k ? r ph pull-up resistor value reset v cc = 3.0 v, v i = 0 v 25 60 130 k ? r pl pull-down resistor value reset v cc = 3.0 v, v i = 3.0 v 7.0 k ? v ram1 ram1 hold voltage (v cc ) when clock stopped 1.1 3.6 v v ram2 ram2 hold voltage (v ddr ) when clock stopped and reset by voltage drop detection 1.1 v http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 52 of 59 rej03b0140-0106 7545 group electrical characte ristics (continued) timing requirements switching characteristics note: 1. pin x out is excluded table 14 electrical characteristics (2) (v cc = 1.8 to 3.6 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. i cc power source current v cc = 3.0 v, f(x in ) = 4 mhz output transistors ? off ? 0.6 1.2 ma v cc = 3.0 v, f(x in ) = 4 mhz (in wit state), functions except timer 1 disabled, output transistors ? off ? 0.3 0.6 ma all oscillation stopped (in stp state) output transistors ? off ? v cc v ddr v cc ? 0.6 v ta = 2 5 c0.11.0 a ta = 8 5 c 10.0 a i ddr during reset by voltage drop detection circuit v ddr = 1.1 v, 1.8 v v cc 0 v ta = 2 5 c0.11.0 a ta = 8 5 c 10.0 a table 15 timing requirements (v cc = 1.8 to 3.6 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. tw(reset ) reset input ? l ? pulse width 2 s t c (x in ) external clock input cycle time 250 ns t wh (x in ) external clock input ? h ? pulse width 100 ns t wl (x in ) external clock input ? l ? pulse width 100 ns t wh (int 0 ) int 0 , int 1 , input ? h ? pulse width 460 ns t wl (int 0 ) int 0 , int 1 , input ? l ? pulse width 460 ns table 16 switching characteristics (v cc = 1.8 to 3.6 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t r (cmos) cmos output rising time (1) 25 100 ns t f (cmos) cmos output falling time (1) 25 100 ns http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 53 of 59 rej03b0140-0106 7545 group fig 58. timing chart 0.2v cc t wl (int 0 ) 0.8v cc t wh (int 0 ) 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w(reset) reset int 0, int 1 http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 54 of 59 rej03b0140-0106 7545 group package outline 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark * 3 f 32 25 24 17 16 9 8 1 * 1 * 2 x b p e h e e d h d z d z e detail f l 1 l a c a 2 a 1 previous code jeita package code renesas code plqp0032gb-a 32p6u-a mass[typ.] 0.2g p-lqfp32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section b 1 c 1 bp c jeita package code p-lssop32-5.6x11-0.65 renesas code plsp0032jb-a previous code 32p2x-b mass [typ.] 0.18 g http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 55 of 59 rej03b0140-0106 7545 group appendix notes on programming processor status register 1. initializing of processor status register flags which affect program execution must be initialized after a reset. in particular, it is essential to initialize the t and d flags because they have an important effect on calculations. after a reset, the contents of the processor status register (ps) are undefined except for the i flag which is ?1?. fig 1. initialization of processor status register 2. how to reference the processor status register to reference the contents of the processor status register (ps), execute the php instruction once then read the contents of (s+1). if necessary, execute the plp instru ction to return the ps to its original status. fig 2. stack memory contents after php instruction execution decimal calculations 1. execution of decimal calculations the adc and sbc are the only instructions which will yield proper decimal notation, set the decimal mode flag (d) to ?1? with the sed instruction. af ter executing the adc or sbc instruction, execute another in struction before executing the sec, clc, or cld instruction. 2. notes on status flag in decimal mode when decimal mode is selected, the values of three of the flags in the status register (the n, v, and z flags) are invalid after a adc or sbc instruction is executed. the carry flag (c) is set to ?1? if a carry is generated as a result of the calculation, or is cleared to ?0? if a borrow is generated. to determine whether a calcula tion has generated a carry, the c flag must be initialized to ?0? before each calculation. to check for a borrow, the c flag must be initialized to ?1? before each calculation. fig 3. status flag at decimal calculations 3. jmp instruction when using the jmp instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4. multiplication and division instructions (1) the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. (2) the execution of these instructions does not change the contents of the proces sor status register. initializing of flags main program reset (s) (s)+1 stored ps adc or sbc instruction nop instruction set d flag to ?g 1 ?h sec, clc, or cld instruction http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 56 of 59 rej03b0140-0106 7545 group 5. read-modify-write instruction do not execute a read-modify-w rite instruction to the read invalid address (sfr). the read-modify-write instruc tion operates in the following sequence: read one-byte of data from memory, modify the data, write the data back to original memory. the following instructions are classified as the read-modify-wr ite instructions in the 740 family. (1) bit management in structions: clb, seb (2) shift and rotate instructions: asl, lsr, rol, ror, rrf (3) add and subtract in structions: dec, inc (4) logical operation instructi ons (1?s complement): com add and subtract/logical oper ation instructions (adc, sbc, and, eor, and ora) when t flag = ?1? operate in the way as the read-modify-write instruc tion. do not execute the read invalid sfr. when the read-modif y-write instruction is executed to read invalid sfr, the instructio n may cause the following consequence: the instruction read s unspecified data from the area due to the read invalid condition. then the instruction modifies this unspecified data and writes the data to the area. the result will be random data written to the area or some unexpected event. notes on peripheral functions notes on i/o ports 1. pull-up control register when using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected. pull-up control is effective only when each direction register is set to the input mode. 2. notes in stand-by state in stand-by state*1 for low-powe r dissipation, do not make input levels of an input port and an i/o port ?undefined?. pull-up (connect the port to vcc) or pull-down (connect the port to vss) these ports through a resistor. when determining a resistance value, note the following points: ? external circuit ? variation of output levels during the ordinary operation when using a built-in pull-up resistor, note on varied current values: ? when setting as an input port : fix its input level ? when setting as an output port : prevent current from flowing out to external. the output transistor becomes th e off state, which causes the ports to be the high-impedance stat e. note that the level becomes ?undefined? depending on external circuits. accordingly, the potent ial which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input port and an i/o port ar e ?undefined?. this may cause power source current. *1 stand-by state : the stop mode by executing the stp instruction 3. modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction*1 , the value of the unspecified bit may be changed. i/o ports are set to input or out put mode in bit units. reading from a port register or writi ng to it involves the following operations. ? port in input mode read: read the pin level. write: write to the port latch. ? port in output mode read: read the port latch or read the output from the peripheral function (specifications differ depending on the port). write: write to the port latch. (the port latch value is output from the pin.) since bit managing instructions*1 are read-modify-write instructions,*2 using such an in struction on a port register causes a read and write to be performed simultaneously on the bits other than the one specified by the instruction. when an unspecified bit is in input mode, its pin level is read and that value is written to the port latch. if the previous value of the port latch differs from the pin level, the port latch value is changed. if an unspecified bit is in output mode, the port latch is generally read. however, for some ports the peripheral function output is read, and the value is written to the port latch. in this case, if the previous value of the port latch differs from the peripheral function output, the port latch value is changed. *1 bit managing instructions : seb and clb instructions *2 read-modify-write instruc tions: instructions that read memory in byte units, modify the value, and then write the result to the same location in memory in byte units 4. direction register the values of the port direct ion registers cannot be read. that is, it is impossible to use the lda instruction, memory operation instruction when the t flag is ?1?, addressing mode using direction regist er values as quali fiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructi ons such as clb and seb and read-modify-write instructions of direction registers for calculat ions such as ror. for setting direction registers, use the ldm instruction, sta instruction, etc. http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 57 of 59 rej03b0140-0106 7545 group termination of unused pins 1. terminate unused pins perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. (1) i/o ports set the i/o ports for the input mo de and connect each pin to v cc or v ss through each resistor of 1 k ? to 10 k ? . the port which can select a built-in pull-up resist or can also use the built-in pull- up resistor. when using the i/o ports as the output mode, open them at ?l? or ?h?. ? when opening them in the output mode, the input mode of the initial status remains until the m ode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroug hly perform syst em evaluation on the user side. ? since the direction register se tup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. 2. termination remarks (1) i/o ports setting as input mode (1) do not open in the input mode. ? the power source current may increase depending on the first- stage circuit. ? an effect due to noise may be easily produced as compared with proper termination (1) s hown on the above ?1. terminate unused pins?. (2) do not connect to v cc or v ss directly. if the direction register set up changes for the output mode because of a program runaway or noise, a short circuit may occur. (3) do not connect multiple ports in a lump to v cc or v ss through a resistor. if the direction register set up changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. notes on interrupts 1. change of relevant register settings when not requiring for the interrupt occurrence synchronous with the following case, take the sequence shown in figure 4. ? when switching external interrupt active edge ? when switching interrupt sources of an interrupt vector address where two or more in terrupt sources are allocated fig 4. sequence of changing relevant register when setting the followings, the interrupt request bit of the corresponding interrupt may be set to ?1?. ? when switching external interrupt active edge int 0 interrupt edge selection bi t (bit 0 of interrupt edge selection register (address 3a 16 )) int 1 interrupt edge selection bi t (bit 1 of interrupt edge selection register) key-on wakeup edge selec tion register (address 19 16 ) 2. check of interrupt request bit when executing the bbc or bbs instruction to determine an interrupt request bit immediately after this bit is set to ?0?, take the following sequence. if the bbc or bbs instruction is executed immediately after an interrupt request bit is cleared to ?0?, the value of the interrupt request bit before being cleared to ?0? is read. fig 5. sequence of check of interrupt request bit set the interrupt edge selection bit, active edge switch bit, or the interrupt source selection bit. nop (one or more instructions) set the corresponding interrupt request bit to ?g 0 ?h (no interrupt request issued). set the corresponding interrupt enable bit to ?g 0 ?h (disabled). set the corresponding interrupt enable bit to ?g 1 ?h (enabled). set the interrupt request bit to ?g 0 ?h (no interrupt issued) nop (one or more instructions) execute the bbc or bbs instruction http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 58 of 59 rej03b0140-0106 7545 group notes on timers 1. when n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). 2. timer count source stop timer 2, timer 3 counting to change its count source. 3. timer 1, timer 2, timer 3 count start timing and count time when operation starts time to first underflow is different from time among next underflow by the timing to st art the timer and count source operations after count starts. 4. timer 2, timer 3, carrier wave generating circuit the timing adjustment of the output waveform causes the gap between the timer c ount value and the output waveform, and the output waveform changes in the reload cycle after the timer underflow. moreover, the timer interrupt occurs at the change point of the output waveform. (the timing of the interrupt occurrence is behind a half cycle of the count source, compared with timer 1. ) notes on watchdog timer 1. the watchdog timer is operat ing during the wait mode. write data to the watchdog timer control register to prevent timer underflow. 2. the watchdog timer stops durin g the stop mode. however, the watchdog timer is runnin g during the oscillation stabi- lizing time after the stp instru ction is released. in order to avoid the underflow of the watchdog timer, the watchdog timer h count source selection bit (bit 7 of watchdog timer control register (address 39 16 )) must be set to ?0? just before executing the stp instruction. notes on reset pin (1) connecting capacitor in case where the reset signal rise time is long, connect a ceramic capacitor or others across the reset pin and the vss pin. and use a 1000 pf or more ca pacitor for high frequency use. when connecting the capaci tor, note the following : ? make the length of the wiring which is connected to a capacitor as short as possible. ? be sure to verify the operatio n of application products on the user side. if the several nanosecond or se veral ten nanosecond impulse noise enters the reset pin, it may cause a microcomputer failure. notes on power-on reset circuit reset occurs by the power-on re set circuit under the following conditions; ? when the power source voltage rises from 0 v to 1.8 v within 1 ms. also, note that reset may not occur under the following conditions; ? when the power source voltage rises from the voltage higher than 0 v. ? when it takes longer than 1 ms that the power source voltage rises from 0 v to 1.8 v. note on voltage drop detection circuit the voltage drop detection circ uit detection voltage of this product is set up lower than th e minimum value of the supply voltage of the recommende d operating conditions. when the supply voltage of a mic rocomputer falls below to the minimum value of recommende d operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the fo llowing case may cause program failure ; supply voltage does not fall below to v det , and its voltage re- goes up with no reset. in such a case, please design a system which supply voltage is once reduced below to v det and re-goes up after that. fig 6. v cc and v det notes on clock generating circuit (1) cpu mode register processor mode bits (bits 1 and 0) of cpu mode register (address 3b 16 ) is used to control operati on modes of the microcomputer. in order to prevent the dead-l ock by erroneously writing (ex. program run-away), these bits can be rewritte n only once after releasing reset. after rewriting, it is disabled to write any data to the bit. (the emulator mcu ?m37545r lss? is excluded.) also, when the read-modify-write instructions (seb, clb, etc.) are executed to bits 2, 6, 7, bits 1 and 0 are locked. (2) ceramic resonator when the ceramic resonator/quartz- crystal oscillation is used for the main clock, connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. a feedback resistor is built-in. vcc v det reset normal operation no reset program failure may occur. recommended o perating condition min. value vcc v det recommended o perating condition min. value http://www..net/ datasheet pdf - http://www..net/
rev.1.06 mar 07, 2008 page 59 of 59 rej03b0140-0106 7545 group notes on oscillation control 1. stop mode (1) when the stop mode is us ed, set ?1? (stp instruction enabled) to the stp instructi on function selection bit (bit 1 of function set rom data (address ffda 16 )). (2) the oscillation stabilizing time after release of stp instruction can be se lected from ?set au tomatically?/?not set automatically? by the oscillation stabilizing time set bit after release of the stp instruc tion (bit 0 of misrg (address 38 16 )). when ?0? is set to this bit, ?03 16 ? is set to timer 1 and ?ff 16 ? is set to prescaler 1 automatically at the execution of the stp instruction. when ?1? is set to this bit, set the wait time to timer 1 and prescaler 1 according to the oscillation stabilizing time of the oscillation. also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is return ed from the stop mode. note on power source voltage when the power source voltage va lue of a microcomputer is less than the value which is indicat ed as the recommended operating conditions, the microc omputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the s upply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. note on product shipped in blank as for the product shipped in blank, renesas does not perform the writing test to user rom area after the assembly process though the qzrom writing test is performed enough before the assembly process. therefore, a writing error of approx.0.1 % may occur. moreover, please note the contact of cables and foreign bodies on a socket, etc. because a wri ting environment may cause some writing errors. precautions regarding overvoltage make sure that voltage exceeding the v cc pin voltage is not applied to other pins. in particular , ensure that the state indicated by bold lines in figure 7 does not occur for pin p4 0 (cnv ss power source pin for qzrom) during power-on or power-off. otherwise the contents of qzrom could be rewritten. fig 7. example of overvoltage data required for qzrom writing orders the following are necessary when ordering a qzrom product shipped after writing: 1. qzrom writing confirmation form* 2. mark specification form* 3. rom data...........mask file * for the qzrom writing confirmation form and the mark specification form, refer to th e ?renesas technology corp.? homepage (http://www.ren esas.com/homepage.jsp). notes on qzrom writing orders when ordering the qzrom product shipped after writing, submit the mask file (extension: .msk) which is made by the mask file converter mm. be sure to set the rom option se tup data (referred to as ?mask option setup data? in mm) when ma king the mask file by using the mask file converter mm. notes on rom code protect (qzrom product shipped after writing) as for the qzrom product shippe d after writing, the rom code protect is specified according to the rom option setup data in the mask file which is submitted at ordering. renesas technology corp. write the value of the rom option setup data in the rom code protect address (address ffdb 16 ) when writing to the qzrom. as a result, in the contents of the rom code protect address the orde red value may differ from the actual written value. the rom option setup data in the mask file is ?00 16 ? for protect enabled or ?ff 16 ? for protect disabled. therefore, the contents of the rom code protect address of the qzrom product shipped after writing is ?00 16 ? or ?ff 16 ?. if you set except ?00 16 ? and ?ff 16 ? or nothing at the rom option data, we cannot ge nerate the rom data. notes on hardware handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (v cc pin, v ddr pin) and gnd pin (v ss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be loca ted too far from the pins to be connected, a ceramic capacitor of 0.1 f is recommended. handling of cnv ss pin the cnv ss pin is connected to the in ternal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, make the length of wiring between the cnv ss pin and the v ss pin the shortest possible. v cc pin voltage cnv ss pin voltage ?l? input (1) input voltage to other mcu pins rises before vcc pin voltage. (2) input voltage to other mcu pins falls after vcc pin voltage. note: the internal circuitry is unstable when vcc is below the minimum voltage specification of 1.8 v (shaded portion), so particular care should be exercised regarding overvoltage. 1.8v 1.8v ~ ~ ~ ~ http://www..net/ datasheet pdf - http://www..net/
(1/2) revision history 7545 group datasheet rev. date description page summary 1.00 feb. 07, 2005 ? first edition issued 1.01 may. 10, 2005 20 fig.22 : carrier wave auto-control bit; ?1? and ?0? added. 26 standard operation of watchdog timer and operation of stp instruction disable bit: address fff a 16 address ffd a 16 note on watchdog timer 2: ... set to ?1 ? just before ... ... set to ?0 ? just before ... 28 voltage drop detection circuit: address fff a 16 address ffd a 16 33 state transition deleted 36 fig. 51 partly revised 40 table 9: r pl ; v k ? 42 fig. 55: cntr 0 int 0 47 notes on watchdog timer: ... set to ?1 ? just before ... ... set to ?0 ? just before ... notes on clock generating circuit 1: bits 2 to 4 to 7 bits 2, 6, 7 1.02 jul. 20, 2005 all pages rom option function set rom 3 table 1: added. 11 rom code protect address (address ffdb 16 ) added. 16 termination of unused pins added. 35 [rom option data] romop [function set rom] fsrom fig. 42, 43: partly revised. 37 (4) wiring to cnv ss pin (4) wiring to v pp pin 51 data required for qzrom writing orders, notes on qzrom writing orders, notes on rom code protect added. 1.03 oct. 21, 2005 ? stp instruction disable bit stp instruction function selection bit 29 ?operation of stp instruction function selection bit? revised. 30 fig.33 block diagram of watchdog timer and reset circuit ?count start (watchd og timer disable bit (bit 0 of fsrom))? added. 35 function set rom : description revised. fig.42: reserved renesas shipme nt test area ?when the checksum is incl uded in the user progra m, avoid assigning it to these areas.? added to note. fig.43: bit 0, bit 1 and bit 4 of fsrom revised. 1.04 may. 17, 2006 ? ?preliminary? eliminated. 1.05 may. 18, 2006 6 fig.4 ?under development? eliminated. 1.06 feb. 29, 2008 1 revised by additional new products (memory size) 2 fig. 2 is added 3 revised by additional new products (memory size and package) 6 fig. 5 is added 8 revised by additional new products (memor y size, package, fig. 6, and table 4) 12 fig. 9 is revised 13 function set rom area and notes (2) - (5) added clock circuit is deleted from [function set rom data] fsrom notes on use deleted 14 fig. 10 is revised 16 fig.12 added 20 to 24 interrupts is revised whole revision history http://www..net/ datasheet pdf - http://www..net/
(2/2) revision history 7545 group datasheet 1.06 feb. 29, 2008 34 initial value of watchdog timer: description added operation of stp instruction function selection bit deleted stp instruction function selection bit added 35 fig. 35 is revised 38 fig. 42 is revised 40 function set rom is moved to memory (page 13) 40 to 44 qzrom writing mode is added 45 notes on hardware is added 46 (4) wiring to v pp pin: ?v pp ? ?cnv ss ? fig.52 is revised 52 symbol of feed-back resistor value between x in -x out is revised 55 plsp0032jb-a package is added. 56 fig.2, 4, and brk instruction deleted 57 modifying output data with bit managing instruction is revised 59 notes on watchdog timer: 3. is added 60 notes on oscillation control is revised (?1? ?0?) precautions regarding overvoltage is added rev. date description page summary http://www..net/ datasheet pdf - http://www..net/
notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas product s for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of t he use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application ci rcuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attentio n to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the t otal system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding th e suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this do cument or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi gned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of h uman injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion co ntrol, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a r enesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to us e renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renes as semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 2008. renesas technology corp., all rights reserved. printed in japan. colophon .7.2 http://www..net/ datasheet pdf - http://www..net/

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